On 31.07.2015 07:06, Zoltan Gilian wrote: > To circumvent a problem occuring when LINEAR_ALIGNED array mode is > selected on a TEXTURE_2D RAT. > This configuration causes MEM_RAT STORE_TYPED to write to incorrect > locations.
[...] > @@ -715,10 +716,15 @@ static unsigned r600_choose_tiling(struct > r600_common_screen *rscreen, > if (templ->flags & R600_RESOURCE_FLAG_TRANSFER) > return RADEON_SURF_MODE_LINEAR_ALIGNED; > > + /* Force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */ > + if ((templ->target == PIPE_TEXTURE_2D || > + templ->target == PIPE_TEXTURE_3D) && > + (templ->bind & PIPE_BIND_COMPUTE_RESOURCE)) > + force_tiling = true; This should test (templ->bind & PIPE_BIND_COMPUTE_RESOURCE) first. Also, does the same restriction apply to SI and newer GPUs? -- Earthling Michel Dänzer | http://www.amd.com Libre software enthusiast | Mesa and X developer _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
