On Mon, Jul 13, 2015 at 02:52:00PM -0700, Matt Turner wrote:
> --- a/src/mesa/drivers/dri/i965/brw_urb.c
> +++ b/src/mesa/drivers/dri/i965/brw_urb.c
> @@ -252,7 +252,7 @@ void brw_upload_urb_fence(struct brw_context *brw)
> if ((USED_BATCH(brw->batch) & 15) > 12) {
> int pad = 16 - (USED_BATCH(brw->batch) & 15);
> do
> - brw->batch.map[brw->batch.used++] = MI_NOOP;
> + *brw->batch.map_next++ = MI_NOOP;
> while (--pad);
This is the only one where I did something different, but it matters
not. We know the brw->batch.map is page aligned so here we can just
inspect the address directly rather than the offset, and then went with
memset(map, 0, pad); map += pad.
The rest looks fine, I had qualms about not
> -#define BEGIN_BATCH_BLT_TILED(n, dst_y_tiled, src_y_tiled) do { \
> +#define BEGIN_BATCH_BLT_TILED(n, dst_y_tiled, src_y_tiled) \
> BEGIN_BATCH_BLT(n + ((dst_y_tiled || src_y_tiled) ? 14 : 0)); \
> if (dst_y_tiled || src_y_tiled) \
> - set_blitter_tiling(brw, dst_y_tiled, src_y_tiled); \
> - } while (0)
> + SET_BLITTER_TILING(brw, dst_y_tiled, src_y_tiled)
using braces around the if () inside this macro, but
if ()
BEGIN_BATCH_TILED
else
something();
won't compile anyway.
For the series then,
Reviewed-by: Chris Wilson <ch...@chris-wilson.co.uk>
It's worth Martin to also review/test as well.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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