Jason Ekstrand <ja...@jlekstrand.net> writes: > Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> > Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com> > --- > src/mesa/drivers/dri/i965/brw_fs.cpp | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp > b/src/mesa/drivers/dri/i965/brw_fs.cpp > index 589b74c..6cf9e96 100644 > --- a/src/mesa/drivers/dri/i965/brw_fs.cpp > +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp > @@ -726,6 +726,12 @@ fs_inst::regs_read(int arg) const > return exec_size / 4; > break; > > + case FS_OPCODE_PIXEL_X: > + case FS_OPCODE_PIXEL_Y: > + if (arg == 0) > + return 2; > + break; > +
This doesn't look right. AFAICT PIXEL_X/Y take two exec_size-wide components of UW type (interleaved for each subspan, but that doesn't matter here), i.e. two registers in SIMD16 mode but only one register in SIMD8 mode. > default: > if (is_tex() && arg == 0 && src[0].file == GRF) > return mlen; > -- > 2.4.3 > > _______________________________________________ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/mesa-dev
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