Jason Ekstrand <ja...@jlekstrand.net> writes: > We want to move these into the builder so that they know the current > builder's dispatch width. This will be needed by a later commit.
I very much like the idea of this series, but, why do you need to move
these register manipulators into the builder? The builder is an object
you can use to:
- Manipulate and query parameters affecting code generation.
- Create instructions into the program (::emit and friends).
- Allocate virtual registers from the program (::vgrf and friends).
offset() and half() logically perform an action on a given register
object (or rather, compute a function of a given register object), not
on a builder object, the builder is only required as an auxiliary
parameter -- Any reason you didn't just pass it as a third parameter?
As offset() and half() don't require access to any private details of
the builder, that would actually improve encapsulation, and would avoid
the dubious overloading of fs_builder::half() with two methods with
completely different semantics.
Thanks.
> ---
> src/mesa/drivers/dri/i965/brw_fs.cpp | 52 ++++++----
> src/mesa/drivers/dri/i965/brw_fs_builder.h | 46 +++++++++
> src/mesa/drivers/dri/i965/brw_fs_cse.cpp | 2 +-
> src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 60 +++++------
> src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 149
> ++++++++++++++-------------
> src/mesa/drivers/dri/i965/brw_ir_fs.h | 51 ---------
> 6 files changed, 182 insertions(+), 178 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
> b/src/mesa/drivers/dri/i965/brw_fs.cpp
> index 4f98d63..c13ac7d 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
> @@ -267,7 +267,7 @@ fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
> &bld,
> inst->mlen = 1 + dispatch_width / 8;
> }
>
> - bld.MOV(dst, offset(vec4_result, (const_offset & 3) * scale));
> + bld.MOV(dst, bld.offset(vec4_result, (const_offset & 3) * scale));
> }
>
> /**
> @@ -361,7 +361,12 @@ fs_inst::is_copy_payload(const brw::simple_allocator
> &grf_alloc) const
> reg.width = this->src[i].width;
> if (!this->src[i].equals(reg))
> return false;
> - reg = ::offset(reg, 1);
> +
> + if (i < this->header_size) {
> + reg.reg_offset += 1;
> + } else {
> + reg.reg_offset += this->exec_size / 8;
> + }
> }
>
> return true;
> @@ -963,7 +968,7 @@ fs_visitor::emit_fragcoord_interpolation(bool
> pixel_center_integer,
> } else {
> bld.ADD(wpos, this->pixel_x, fs_reg(0.5f));
> }
> - wpos = offset(wpos, 1);
> + wpos = bld.offset(wpos, 1);
>
> /* gl_FragCoord.y */
> if (!flip && pixel_center_integer) {
> @@ -979,7 +984,7 @@ fs_visitor::emit_fragcoord_interpolation(bool
> pixel_center_integer,
>
> bld.ADD(wpos, pixel_y, fs_reg(offset));
> }
> - wpos = offset(wpos, 1);
> + wpos = bld.offset(wpos, 1);
>
> /* gl_FragCoord.z */
> if (devinfo->gen >= 6) {
> @@ -989,7 +994,7 @@ fs_visitor::emit_fragcoord_interpolation(bool
> pixel_center_integer,
> this->delta_xy[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
> interp_reg(VARYING_SLOT_POS, 2));
> }
> - wpos = offset(wpos, 1);
> + wpos = bld.offset(wpos, 1);
>
> /* gl_FragCoord.w: Already set up in emit_interpolation */
> bld.MOV(wpos, this->wpos_w);
> @@ -1072,7 +1077,7 @@ fs_visitor::emit_general_interpolation(fs_reg attr,
> const char *name,
> /* If there's no incoming setup data for this slot, don't
> * emit interpolation for it.
> */
> - attr = offset(attr, type->vector_elements);
> + attr = bld.offset(attr, type->vector_elements);
> location++;
> continue;
> }
> @@ -1087,7 +1092,7 @@ fs_visitor::emit_general_interpolation(fs_reg attr,
> const char *name,
> interp = suboffset(interp, 3);
> interp.type = attr.type;
> bld.emit(FS_OPCODE_CINTERP, attr, fs_reg(interp));
> - attr = offset(attr, 1);
> + attr = bld.offset(attr, 1);
> }
> } else {
> /* Smooth/noperspective interpolation case. */
> @@ -1125,7 +1130,7 @@ fs_visitor::emit_general_interpolation(fs_reg attr,
> const char *name,
> if (devinfo->gen < 6 && interpolation_mode ==
> INTERP_QUALIFIER_SMOOTH) {
> bld.MUL(attr, attr, this->pixel_w);
> }
> - attr = offset(attr, 1);
> + attr = bld.offset(attr, 1);
> }
>
> }
> @@ -1227,19 +1232,19 @@ fs_visitor::emit_samplepos_setup()
> if (dispatch_width == 8) {
> abld.MOV(int_sample_x, fs_reg(sample_pos_reg));
> } else {
> - abld.half(0).MOV(half(int_sample_x, 0), fs_reg(sample_pos_reg));
> - abld.half(1).MOV(half(int_sample_x, 1),
> + abld.half(0).MOV(abld.half(int_sample_x, 0), fs_reg(sample_pos_reg));
> + abld.half(1).MOV(abld.half(int_sample_x, 1),
> fs_reg(suboffset(sample_pos_reg, 16)));
> }
> /* Compute gl_SamplePosition.x */
> compute_sample_position(pos, int_sample_x);
> - pos = offset(pos, 1);
> + pos = abld.offset(pos, 1);
> if (dispatch_width == 8) {
> abld.MOV(int_sample_y, fs_reg(suboffset(sample_pos_reg, 1)));
> } else {
> - abld.half(0).MOV(half(int_sample_y, 0),
> + abld.half(0).MOV(abld.half(int_sample_y, 0),
> fs_reg(suboffset(sample_pos_reg, 1)));
> - abld.half(1).MOV(half(int_sample_y, 1),
> + abld.half(1).MOV(abld.half(int_sample_y, 1),
> fs_reg(suboffset(sample_pos_reg, 17)));
> }
> /* Compute gl_SamplePosition.y */
> @@ -3018,10 +3023,6 @@ fs_visitor::lower_load_payload()
>
> assert(inst->dst.file == MRF || inst->dst.file == GRF);
> assert(inst->saturate == false);
> -
> - const fs_builder ibld = bld.group(inst->exec_size, inst->force_sechalf)
> - .exec_all(inst->force_writemask_all)
> - .at(block, inst);
> fs_reg dst = inst->dst;
>
> /* Get rid of COMPR4. We'll add it back in if we need it */
> @@ -3029,17 +3030,23 @@ fs_visitor::lower_load_payload()
> dst.reg = dst.reg & ~BRW_MRF_COMPR4;
>
> dst.width = 8;
> + const fs_builder hbld = bld.group(8, 0).exec_all().at(block, inst);
> +
> for (uint8_t i = 0; i < inst->header_size; i++) {
> if (inst->src[i].file != BAD_FILE) {
> fs_reg mov_dst = retype(dst, BRW_REGISTER_TYPE_UD);
> fs_reg mov_src = retype(inst->src[i], BRW_REGISTER_TYPE_UD);
> mov_src.width = 8;
> - ibld.exec_all().MOV(mov_dst, mov_src);
> + hbld.MOV(mov_dst, mov_src);
> }
> - dst = offset(dst, 1);
> + dst = hbld.offset(dst, 1);
> }
>
> dst.width = inst->exec_size;
> + const fs_builder ibld = bld.group(inst->exec_size, inst->force_sechalf)
> + .exec_all(inst->force_writemask_all)
> + .at(block, inst);
> +
> if (inst->dst.file == MRF && (inst->dst.reg & BRW_MRF_COMPR4) &&
> inst->exec_size > 8) {
> /* In this case, the payload portion of the LOAD_PAYLOAD isn't
> @@ -3070,8 +3077,9 @@ fs_visitor::lower_load_payload()
> /* Platform doesn't have COMPR4. We have to fake it */
> fs_reg mov_dst = retype(dst, inst->src[i].type);
> mov_dst.width = 8;
> - ibld.half(0).MOV(mov_dst, half(inst->src[i], 0));
> - ibld.half(1).MOV(offset(mov_dst, 4), half(inst->src[i],
> 1));
> + ibld.half(0).MOV(mov_dst, ibld.half(inst->src[i], 0));
> + mov_dst.reg += 4;
> + ibld.half(1).MOV(mov_dst, ibld.half(inst->src[i], 1));
> }
> }
>
> @@ -3096,7 +3104,7 @@ fs_visitor::lower_load_payload()
> for (uint8_t i = inst->header_size; i < inst->sources; i++) {
> if (inst->src[i].file != BAD_FILE)
> ibld.MOV(retype(dst, inst->src[i].type), inst->src[i]);
> - dst = offset(dst, 1);
> + dst = ibld.offset(dst, 1);
> }
>
> inst->remove(block);
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_builder.h
> b/src/mesa/drivers/dri/i965/brw_fs_builder.h
> index 58ac598..594e252 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_builder.h
> +++ b/src/mesa/drivers/dri/i965/brw_fs_builder.h
> @@ -151,6 +151,52 @@ namespace brw {
> return _dispatch_width;
> }
>
> + src_reg
> + offset(src_reg reg, unsigned delta) const
> + {
> + switch (reg.file) {
> + case BAD_FILE:
> + break;
> + case GRF:
> + case MRF:
> + case ATTR:
> + return byte_offset(reg,
> + delta * MAX2(reg.width * reg.stride, 1) *
> + type_sz(reg.type));
> + case UNIFORM:
> + reg.reg_offset += delta;
> + break;
> + default:
> + assert(delta == 0);
> + }
> + return reg;
> + }
> +
> + fs_reg
> + half(fs_reg reg, unsigned idx) const
> + {
> + assert(idx < 2);
> +
> + switch (reg.file) {
> + case BAD_FILE:
> + case UNIFORM:
> + case IMM:
> + return reg;
> +
> + case GRF:
> + case MRF:
> + assert(reg.width == 16);
> + reg.width = 8;
> + return horiz_offset(reg, 8 * idx);
> +
> + case ATTR:
> + case HW_REG:
> + default:
> + unreachable("Cannot take half of this register type");
> + }
> + return reg;
> + }
> +
> /**
> * Allocate a virtual register of natural vector size (one for this IR)
> * and SIMD width. \p n gives the amount of space to allocate in
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
> index 70f0217..5ea66c5 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
> @@ -205,7 +205,7 @@ create_copy_instr(const fs_builder &bld, fs_inst *inst,
> fs_reg src, bool negate)
> }
> for (int i = header_size; i < sources; i++) {
> payload[i] = src;
> - src = offset(src, 1);
> + src = ubld.offset(src, 1);
> }
> copy = ubld.LOAD_PAYLOAD(inst->dst, payload, sources, header_size);
> } else {
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> index 59081ea..0ede634 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> @@ -76,7 +76,7 @@ fs_visitor::nir_setup_inputs(nir_shader *shader)
> {
> foreach_list_typed(nir_variable, var, node, &shader->inputs) {
> enum brw_reg_type type = brw_type_for_base_type(var->type);
> - fs_reg input = offset(nir_inputs, var->data.driver_location);
> + fs_reg input = bld.offset(nir_inputs, var->data.driver_location);
>
> fs_reg reg;
> switch (stage) {
> @@ -95,8 +95,8 @@ fs_visitor::nir_setup_inputs(nir_shader *shader)
> unsigned array_length = var->type->is_array() ? var->type->length :
> 1;
> for (unsigned i = 0; i < array_length; i++) {
> for (unsigned j = 0; j < components; j++) {
> - bld.MOV(retype(offset(input, components * i + j), type),
> - offset(fs_reg(ATTR, var->data.location + i, type),
> j));
> + bld.MOV(retype(bld.offset(input, components * i + j), type),
> + bld.offset(fs_reg(ATTR, var->data.location + i,
> type), j));
> }
> }
> break;
> @@ -127,7 +127,7 @@ fs_visitor::nir_setup_outputs(nir_shader *shader)
> brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
>
> foreach_list_typed(nir_variable, var, node, &shader->outputs) {
> - fs_reg reg = offset(nir_outputs, var->data.driver_location);
> + fs_reg reg = bld.offset(nir_outputs, var->data.driver_location);
>
> int vector_elements =
> var->type->is_array() ? var->type->fields.array->vector_elements
> @@ -136,7 +136,7 @@ fs_visitor::nir_setup_outputs(nir_shader *shader)
> if (stage == MESA_SHADER_VERTEX) {
> for (int i = 0; i < ALIGN(type_size(var->type), 4) / 4; i++) {
> int output = var->data.location + i;
> - this->outputs[output] = offset(reg, 4 * i);
> + this->outputs[output] = bld.offset(reg, 4 * i);
> this->output_components[output] = vector_elements;
> }
> } else if (var->data.index > 0) {
> @@ -162,7 +162,7 @@ fs_visitor::nir_setup_outputs(nir_shader *shader)
> /* General color output. */
> for (unsigned int i = 0; i < MAX2(1, var->type->length); i++) {
> int output = var->data.location - FRAG_RESULT_DATA0 + i;
> - this->outputs[output] = offset(reg, vector_elements * i);
> + this->outputs[output] = bld.offset(reg, vector_elements * i);
> this->output_components[output] = vector_elements;
> }
> }
> @@ -618,11 +618,11 @@ fs_visitor::nir_emit_alu(const fs_builder &bld,
> nir_alu_instr *instr)
> continue;
>
> if (instr->op == nir_op_imov || instr->op == nir_op_fmov) {
> - inst = bld.MOV(offset(temp, i),
> - offset(op[0], instr->src[0].swizzle[i]));
> + inst = bld.MOV(bld.offset(temp, i),
> + bld.offset(op[0], instr->src[0].swizzle[i]));
> } else {
> - inst = bld.MOV(offset(temp, i),
> - offset(op[i], instr->src[i].swizzle[0]));
> + inst = bld.MOV(bld.offset(temp, i),
> + bld.offset(op[i], instr->src[i].swizzle[0]));
> }
> inst->saturate = instr->dest.saturate;
> }
> @@ -636,7 +636,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld,
> nir_alu_instr *instr)
> if (!(instr->dest.write_mask & (1 << i)))
> continue;
>
> - bld.MOV(offset(result, i), offset(temp, i));
> + bld.MOV(bld.offset(result, i), bld.offset(temp, i));
> }
> }
> return;
> @@ -657,12 +657,12 @@ fs_visitor::nir_emit_alu(const fs_builder &bld,
> nir_alu_instr *instr)
> assert(_mesa_bitcount(instr->dest.write_mask) == 1);
> channel = ffs(instr->dest.write_mask) - 1;
>
> - result = offset(result, channel);
> + result = bld.offset(result, channel);
> }
>
> for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
> assert(nir_op_infos[instr->op].input_sizes[i] < 2);
> - op[i] = offset(op[i], instr->src[i].swizzle[channel]);
> + op[i] = bld.offset(op[i], instr->src[i].swizzle[channel]);
> }
>
> switch (instr->op) {
> @@ -1156,7 +1156,7 @@ fs_reg_for_nir_reg(fs_visitor *v, nir_register *nir_reg,
> else
> reg = v->nir_locals[nir_reg->index];
>
> - reg = offset(reg, base_offset * nir_reg->num_components);
> + reg = v->bld.offset(reg, base_offset * nir_reg->num_components);
> if (indirect) {
> int multiplier = nir_reg->num_components * (v->dispatch_width / 8);
>
> @@ -1177,7 +1177,7 @@ fs_visitor::get_nir_src(nir_src src)
> fs_reg reg = bld.vgrf(BRW_REGISTER_TYPE_D, src.ssa->num_components);
>
> for (unsigned i = 0; i < src.ssa->num_components; ++i)
> - bld.MOV(offset(reg, i), fs_reg(load->value.i[i]));
> + bld.MOV(bld.offset(reg, i), fs_reg(load->value.i[i]));
>
> return reg;
> } else {
> @@ -1208,10 +1208,10 @@ fs_visitor::emit_percomp(const fs_builder &bld, const
> fs_inst &inst,
> continue;
>
> fs_inst *new_inst = new(mem_ctx) fs_inst(inst);
> - new_inst->dst = offset(new_inst->dst, i);
> + new_inst->dst = bld.offset(new_inst->dst, i);
> for (unsigned j = 0; j < new_inst->sources; j++)
> if (new_inst->src[j].file == GRF)
> - new_inst->src[j] = offset(new_inst->src[j], i);
> + new_inst->src[j] = bld.offset(new_inst->src[j], i);
>
> bld.emit(new_inst);
> }
> @@ -1322,7 +1322,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld,
> nir_intrinsic_instr *instr
> assert(sample_pos.file != BAD_FILE);
> dest.type = sample_pos.type;
> bld.MOV(dest, sample_pos);
> - bld.MOV(offset(dest, 1), offset(sample_pos, 1));
> + bld.MOV(bld.offset(dest, 1), bld.offset(sample_pos, 1));
> break;
> }
>
> @@ -1349,13 +1349,13 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld,
> nir_intrinsic_instr *instr
> }
>
> for (unsigned j = 0; j < instr->num_components; j++) {
> - fs_reg src = offset(retype(uniform_reg, dest.type), index);
> + fs_reg src = bld.offset(retype(uniform_reg, dest.type), index);
> if (has_indirect)
> src.reladdr = new(mem_ctx) fs_reg(get_nir_src(instr->src[0]));
> index++;
>
> bld.MOV(dest, src);
> - dest = offset(dest, 1);
> + dest = bld.offset(dest, 1);
> }
> break;
> }
> @@ -1397,7 +1397,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld,
> nir_intrinsic_instr *instr
>
> unsigned vec4_offset = instr->const_index[0] / 4;
> for (int i = 0; i < instr->num_components; i++)
> - VARYING_PULL_CONSTANT_LOAD(bld, offset(dest, i), surf_index,
> + VARYING_PULL_CONSTANT_LOAD(bld, bld.offset(dest, i), surf_index,
> base_offset, vec4_offset + i);
> } else {
> fs_reg packed_consts = vgrf(glsl_type::float_type);
> @@ -1416,7 +1416,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld,
> nir_intrinsic_instr *instr
> assert(packed_consts.subreg_offset < 32);
>
> bld.MOV(dest, packed_consts);
> - dest = offset(dest, 1);
> + dest = bld.offset(dest, 1);
> }
> }
> break;
> @@ -1428,14 +1428,14 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld,
> nir_intrinsic_instr *instr
> case nir_intrinsic_load_input: {
> unsigned index = 0;
> for (unsigned j = 0; j < instr->num_components; j++) {
> - fs_reg src = offset(retype(nir_inputs, dest.type),
> + fs_reg src = bld.offset(retype(nir_inputs, dest.type),
> instr->const_index[0] + index);
> if (has_indirect)
> src.reladdr = new(mem_ctx) fs_reg(get_nir_src(instr->src[0]));
> index++;
>
> bld.MOV(dest, src);
> - dest = offset(dest, 1);
> + dest = bld.offset(dest, 1);
> }
> break;
> }
> @@ -1508,7 +1508,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld,
> nir_intrinsic_instr *instr
> BRW_REGISTER_TYPE_F);
> for (int i = 0; i < 2; i++) {
> fs_reg temp = vgrf(glsl_type::float_type);
> - bld.MUL(temp, offset(offset_src, i), fs_reg(16.0f));
> + bld.MUL(temp, bld.offset(offset_src, i), fs_reg(16.0f));
> fs_reg itemp = vgrf(glsl_type::int_type);
> bld.MOV(itemp, temp); /* float to int */
>
> @@ -1528,7 +1528,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld,
> nir_intrinsic_instr *instr
> * FRAGMENT_INTERPOLATION_OFFSET_BITS"
> */
> set_condmod(BRW_CONDITIONAL_L,
> - bld.SEL(offset(src, i), itemp, fs_reg(7)));
> + bld.SEL(bld.offset(src, i), itemp, fs_reg(7)));
> }
>
> mlen = 2;
> @@ -1552,7 +1552,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld,
> nir_intrinsic_instr *instr
> src.type = dest.type;
>
> bld.emit(FS_OPCODE_LINTERP, dest, dst_xy, src);
> - dest = offset(dest, 1);
> + dest = bld.offset(dest, 1);
> }
> break;
> }
> @@ -1564,13 +1564,13 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld,
> nir_intrinsic_instr *instr
> fs_reg src = get_nir_src(instr->src[0]);
> unsigned index = 0;
> for (unsigned j = 0; j < instr->num_components; j++) {
> - fs_reg new_dest = offset(retype(nir_outputs, src.type),
> - instr->const_index[0] + index);
> + fs_reg new_dest = bld.offset(retype(nir_outputs, src.type),
> + instr->const_index[0] + index);
> if (has_indirect)
> src.reladdr = new(mem_ctx) fs_reg(get_nir_src(instr->src[1]));
> index++;
> bld.MOV(new_dest, src);
> - src = offset(src, 1);
> + src = bld.offset(src, 1);
> }
> break;
> }
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> index 8a43ec8..68cd454 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> @@ -95,7 +95,7 @@ fs_visitor::emit_texture_gen4(ir_texture_opcode op, fs_reg
> dst,
> if (shadow_c.file != BAD_FILE) {
> for (int i = 0; i < coord_components; i++) {
> bld.MOV(fs_reg(MRF, base_mrf + mlen + i), coordinate);
> - coordinate = offset(coordinate, 1);
> + coordinate = bld.offset(coordinate, 1);
> }
>
> /* gen4's SIMD8 sampler always has the slots for u,v,r present.
> @@ -124,7 +124,7 @@ fs_visitor::emit_texture_gen4(ir_texture_opcode op,
> fs_reg dst,
> } else if (op == ir_tex) {
> for (int i = 0; i < coord_components; i++) {
> bld.MOV(fs_reg(MRF, base_mrf + mlen + i), coordinate);
> - coordinate = offset(coordinate, 1);
> + coordinate = bld.offset(coordinate, 1);
> }
> /* zero the others. */
> for (int i = coord_components; i<3; i++) {
> @@ -137,7 +137,7 @@ fs_visitor::emit_texture_gen4(ir_texture_opcode op,
> fs_reg dst,
>
> for (int i = 0; i < coord_components; i++) {
> bld.MOV(fs_reg(MRF, base_mrf + mlen + i), coordinate);
> - coordinate = offset(coordinate, 1);
> + coordinate = bld.offset(coordinate, 1);
> }
> /* the slots for u and v are always present, but r is optional */
> mlen += MAX2(coord_components, 2);
> @@ -158,13 +158,13 @@ fs_visitor::emit_texture_gen4(ir_texture_opcode op,
> fs_reg dst,
> */
> for (int i = 0; i < grad_components; i++) {
> bld.MOV(fs_reg(MRF, base_mrf + mlen), dPdx);
> - dPdx = offset(dPdx, 1);
> + dPdx = bld.offset(dPdx, 1);
> }
> mlen += MAX2(grad_components, 2);
>
> for (int i = 0; i < grad_components; i++) {
> bld.MOV(fs_reg(MRF, base_mrf + mlen), dPdy);
> - dPdy = offset(dPdy, 1);
> + dPdy = bld.offset(dPdy, 1);
> }
> mlen += MAX2(grad_components, 2);
> } else if (op == ir_txs) {
> @@ -182,7 +182,7 @@ fs_visitor::emit_texture_gen4(ir_texture_opcode op,
> fs_reg dst,
> for (int i = 0; i < coord_components; i++) {
> bld.MOV(fs_reg(MRF, base_mrf + mlen + i * 2, coordinate.type),
> coordinate);
> - coordinate = offset(coordinate, 1);
> + coordinate = bld.offset(coordinate, 1);
> }
>
> /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to
> @@ -232,8 +232,8 @@ fs_visitor::emit_texture_gen4(ir_texture_opcode op,
> fs_reg dst,
> if (simd16) {
> for (int i = 0; i < 4; i++) {
> bld.MOV(orig_dst, dst);
> - orig_dst = offset(orig_dst, 1);
> - dst = offset(dst, 2);
> + orig_dst = bld.offset(orig_dst, 1);
> + dst = bld.offset(dst, 2);
> }
> }
>
> @@ -257,30 +257,30 @@ fs_visitor::emit_texture_gen4_simd16(ir_texture_opcode
> op, fs_reg dst,
>
> /* Copy the coordinates. */
> for (int i = 0; i < vector_elements; i++) {
> - bld.MOV(retype(offset(message, i), coordinate.type), coordinate);
> - coordinate = offset(coordinate, 1);
> + bld.MOV(retype(bld.offset(message, i), coordinate.type), coordinate);
> + coordinate = bld.offset(coordinate, 1);
> }
>
> - fs_reg msg_end = offset(message, vector_elements);
> + fs_reg msg_end = bld.offset(message, vector_elements);
>
> /* Messages other than sample and ld require all three components */
> if (has_lod || shadow_c.file != BAD_FILE) {
> for (int i = vector_elements; i < 3; i++) {
> - bld.MOV(offset(message, i), fs_reg(0.0f));
> + bld.MOV(bld.offset(message, i), fs_reg(0.0f));
> }
> }
>
> if (has_lod) {
> - fs_reg msg_lod = retype(offset(message, 3), op == ir_txf ?
> + fs_reg msg_lod = retype(bld.offset(message, 3), op == ir_txf ?
> BRW_REGISTER_TYPE_UD : BRW_REGISTER_TYPE_F);
> bld.MOV(msg_lod, lod);
> - msg_end = offset(msg_lod, 1);
> + msg_end = bld.offset(msg_lod, 1);
> }
>
> if (shadow_c.file != BAD_FILE) {
> - fs_reg msg_ref = offset(message, 3 + has_lod);
> + fs_reg msg_ref = bld.offset(message, 3 + has_lod);
> bld.MOV(msg_ref, shadow_c);
> - msg_end = offset(msg_ref, 1);
> + msg_end = bld.offset(msg_ref, 1);
> }
>
> enum opcode opcode;
> @@ -334,16 +334,16 @@ fs_visitor::emit_texture_gen5(ir_texture_opcode op,
> fs_reg dst,
> }
>
> for (int i = 0; i < vector_elements; i++) {
> - bld.MOV(retype(offset(msg_coords, i), coordinate.type), coordinate);
> - coordinate = offset(coordinate, 1);
> + bld.MOV(retype(bld.offset(msg_coords, i), coordinate.type),
> coordinate);
> + coordinate = bld.offset(coordinate, 1);
> }
> - fs_reg msg_end = offset(msg_coords, vector_elements);
> - fs_reg msg_lod = offset(msg_coords, 4);
> + fs_reg msg_end = bld.offset(msg_coords, vector_elements);
> + fs_reg msg_lod = bld.offset(msg_coords, 4);
>
> if (shadow_c.file != BAD_FILE) {
> fs_reg msg_shadow = msg_lod;
> bld.MOV(msg_shadow, shadow_c);
> - msg_lod = offset(msg_shadow, 1);
> + msg_lod = bld.offset(msg_shadow, 1);
> msg_end = msg_lod;
> }
>
> @@ -354,13 +354,13 @@ fs_visitor::emit_texture_gen5(ir_texture_opcode op,
> fs_reg dst,
> break;
> case ir_txb:
> bld.MOV(msg_lod, lod);
> - msg_end = offset(msg_lod, 1);
> + msg_end = bld.offset(msg_lod, 1);
>
> opcode = FS_OPCODE_TXB;
> break;
> case ir_txl:
> bld.MOV(msg_lod, lod);
> - msg_end = offset(msg_lod, 1);
> + msg_end = bld.offset(msg_lod, 1);
>
> opcode = SHADER_OPCODE_TXL;
> break;
> @@ -377,12 +377,12 @@ fs_visitor::emit_texture_gen5(ir_texture_opcode op,
> fs_reg dst,
> msg_end = msg_lod;
> for (int i = 0; i < grad_components; i++) {
> bld.MOV(msg_end, lod);
> - lod = offset(lod, 1);
> - msg_end = offset(msg_end, 1);
> + lod = bld.offset(lod, 1);
> + msg_end = bld.offset(msg_end, 1);
>
> bld.MOV(msg_end, lod2);
> - lod2 = offset(lod2, 1);
> - msg_end = offset(msg_end, 1);
> + lod2 = bld.offset(lod2, 1);
> + msg_end = bld.offset(msg_end, 1);
> }
>
> opcode = SHADER_OPCODE_TXD;
> @@ -391,31 +391,31 @@ fs_visitor::emit_texture_gen5(ir_texture_opcode op,
> fs_reg dst,
> case ir_txs:
> msg_lod = retype(msg_end, BRW_REGISTER_TYPE_UD);
> bld.MOV(msg_lod, lod);
> - msg_end = offset(msg_lod, 1);
> + msg_end = bld.offset(msg_lod, 1);
>
> opcode = SHADER_OPCODE_TXS;
> break;
> case ir_query_levels:
> msg_lod = msg_end;
> bld.MOV(retype(msg_lod, BRW_REGISTER_TYPE_UD), fs_reg(0u));
> - msg_end = offset(msg_lod, 1);
> + msg_end = bld.offset(msg_lod, 1);
>
> opcode = SHADER_OPCODE_TXS;
> break;
> case ir_txf:
> - msg_lod = offset(msg_coords, 3);
> + msg_lod = bld.offset(msg_coords, 3);
> bld.MOV(retype(msg_lod, BRW_REGISTER_TYPE_UD), lod);
> - msg_end = offset(msg_lod, 1);
> + msg_end = bld.offset(msg_lod, 1);
>
> opcode = SHADER_OPCODE_TXF;
> break;
> case ir_txf_ms:
> - msg_lod = offset(msg_coords, 3);
> + msg_lod = bld.offset(msg_coords, 3);
> /* lod */
> bld.MOV(retype(msg_lod, BRW_REGISTER_TYPE_UD), fs_reg(0u));
> /* sample index */
> - bld.MOV(retype(offset(msg_lod, 1), BRW_REGISTER_TYPE_UD),
> sample_index);
> - msg_end = offset(msg_lod, 2);
> + bld.MOV(retype(bld.offset(msg_lod, 1), BRW_REGISTER_TYPE_UD),
> sample_index);
> + msg_end = bld.offset(msg_lod, 2);
>
> opcode = SHADER_OPCODE_TXF_CMS;
> break;
> @@ -525,7 +525,7 @@ fs_visitor::emit_texture_gen7(ir_texture_opcode op,
> fs_reg dst,
> */
> for (int i = 0; i < coord_components; i++) {
> bld.MOV(sources[length], coordinate);
> - coordinate = offset(coordinate, 1);
> + coordinate = bld.offset(coordinate, 1);
> length++;
>
> /* For cube map array, the coordinate is (u,v,r,ai) but there are
> @@ -533,11 +533,11 @@ fs_visitor::emit_texture_gen7(ir_texture_opcode op,
> fs_reg dst,
> */
> if (i < grad_components) {
> bld.MOV(sources[length], lod);
> - lod = offset(lod, 1);
> + lod = bld.offset(lod, 1);
> length++;
>
> bld.MOV(sources[length], lod2);
> - lod2 = offset(lod2, 1);
> + lod2 = bld.offset(lod2, 1);
> length++;
> }
> }
> @@ -559,13 +559,13 @@ fs_visitor::emit_texture_gen7(ir_texture_opcode op,
> fs_reg dst,
> */
>
> bld.MOV(retype(sources[length], BRW_REGISTER_TYPE_D), coordinate);
> - coordinate = offset(coordinate, 1);
> + coordinate = bld.offset(coordinate, 1);
> length++;
>
> if (devinfo->gen >= 9) {
> if (coord_components >= 2) {
> bld.MOV(retype(sources[length], BRW_REGISTER_TYPE_D),
> coordinate);
> - coordinate = offset(coordinate, 1);
> + coordinate = bld.offset(coordinate, 1);
> }
> length++;
> }
> @@ -575,7 +575,7 @@ fs_visitor::emit_texture_gen7(ir_texture_opcode op,
> fs_reg dst,
>
> for (int i = devinfo->gen >= 9 ? 2 : 1; i < coord_components; i++) {
> bld.MOV(retype(sources[length], BRW_REGISTER_TYPE_D), coordinate);
> - coordinate = offset(coordinate, 1);
> + coordinate = bld.offset(coordinate, 1);
> length++;
> }
>
> @@ -594,7 +594,7 @@ fs_visitor::emit_texture_gen7(ir_texture_opcode op,
> fs_reg dst,
> */
> for (int i = 0; i < coord_components; i++) {
> bld.MOV(retype(sources[length], BRW_REGISTER_TYPE_D), coordinate);
> - coordinate = offset(coordinate, 1);
> + coordinate = bld.offset(coordinate, 1);
> length++;
> }
>
> @@ -608,19 +608,19 @@ fs_visitor::emit_texture_gen7(ir_texture_opcode op,
> fs_reg dst,
> /* More crazy intermixing */
> for (int i = 0; i < 2; i++) { /* u, v */
> bld.MOV(sources[length], coordinate);
> - coordinate = offset(coordinate, 1);
> + coordinate = bld.offset(coordinate, 1);
> length++;
> }
>
> for (int i = 0; i < 2; i++) { /* offu, offv */
> bld.MOV(retype(sources[length], BRW_REGISTER_TYPE_D),
> offset_value);
> - offset_value = offset(offset_value, 1);
> + offset_value = bld.offset(offset_value, 1);
> length++;
> }
>
> if (coord_components == 3) { /* r if present */
> bld.MOV(sources[length], coordinate);
> - coordinate = offset(coordinate, 1);
> + coordinate = bld.offset(coordinate, 1);
> length++;
> }
>
> @@ -633,7 +633,7 @@ fs_visitor::emit_texture_gen7(ir_texture_opcode op,
> fs_reg dst,
> if (!coordinate_done) {
> for (int i = 0; i < coord_components; i++) {
> bld.MOV(sources[length], coordinate);
> - coordinate = offset(coordinate, 1);
> + coordinate = bld.offset(coordinate, 1);
> length++;
> }
> }
> @@ -746,8 +746,8 @@ fs_visitor::rescale_texcoord(fs_reg coordinate, int
> coord_components,
> coordinate = dst;
>
> bld.MUL(dst, src, scale_x);
> - dst = offset(dst, 1);
> - src = offset(src, 1);
> + dst = bld.offset(dst, 1);
> + src = bld.offset(src, 1);
> bld.MUL(dst, src, scale_y);
> } else if (is_rect) {
> /* On gen6+, the sampler handles the rectangle coordinates
> @@ -760,7 +760,7 @@ fs_visitor::rescale_texcoord(fs_reg coordinate, int
> coord_components,
> for (int i = 0; i < 2; i++) {
> if (key_tex->gl_clamp_mask[i] & (1 << sampler)) {
> fs_reg chan = coordinate;
> - chan = offset(chan, i);
> + chan = bld.offset(chan, i);
>
> set_condmod(BRW_CONDITIONAL_GE,
> bld.emit(BRW_OPCODE_SEL, chan, chan, fs_reg(0.0f)));
> @@ -785,7 +785,7 @@ fs_visitor::rescale_texcoord(fs_reg coordinate, int
> coord_components,
> for (int i = 0; i < MIN2(coord_components, 3); i++) {
> if (key_tex->gl_clamp_mask[i] & (1 << sampler)) {
> fs_reg chan = coordinate;
> - chan = offset(chan, i);
> + chan = bld.offset(chan, i);
> set_saturate(true, bld.MOV(chan, chan));
> }
> }
> @@ -807,7 +807,7 @@ fs_visitor::emit_mcs_fetch(fs_reg coordinate, int
> components, fs_reg sampler)
> for (int i = 0; i < components; i++) {
> sources[i] = vgrf(glsl_type::float_type);
> bld.MOV(retype(sources[i], BRW_REGISTER_TYPE_D), coordinate);
> - coordinate = offset(coordinate, 1);
> + coordinate = bld.offset(coordinate, 1);
> }
>
> bld.LOAD_PAYLOAD(payload, sources, components, 0);
> @@ -853,7 +853,7 @@ fs_visitor::emit_texture(ir_texture_opcode op,
>
> for (int i=0; i<4; i++) {
> bld.MOV(res, fs_reg(swiz == SWIZZLE_ZERO ? 0.0f : 1.0f));
> - res = offset(res, 1);
> + res = bld.offset(res, 1);
> }
> return;
> }
> @@ -907,7 +907,7 @@ fs_visitor::emit_texture(ir_texture_opcode op,
>
> /* fixup #layers for cube map arrays */
> if (op == ir_txs && is_cube_array) {
> - fs_reg depth = offset(dst, 2);
> + fs_reg depth = bld.offset(dst, 2);
> fs_reg fixed_depth = vgrf(glsl_type::int_type);
> bld.emit(SHADER_OPCODE_INT_QUOTIENT, fixed_depth, depth, fs_reg(6));
>
> @@ -917,7 +917,7 @@ fs_visitor::emit_texture(ir_texture_opcode op,
> if (i == 2) {
> fixed_payload[i] = fixed_depth;
> } else {
> - fixed_payload[i] = offset(dst, i);
> + fixed_payload[i] = bld.offset(dst, i);
> }
> }
> bld.LOAD_PAYLOAD(dst, fixed_payload, components, 0);
> @@ -952,7 +952,7 @@ fs_visitor::emit_gen6_gather_wa(uint8_t wa, fs_reg dst)
> bld.ASR(dst, dst, fs_reg(32 - width));
> }
>
> - dst = offset(dst, 1);
> + dst = bld.offset(dst, 1);
> }
> }
>
> @@ -989,7 +989,7 @@ fs_visitor::swizzle_result(ir_texture_opcode op, int
> dest_components,
> {
> if (op == ir_query_levels) {
> /* # levels is in .w */
> - this->result = offset(orig_val, 3);
> + this->result = bld.offset(orig_val, 3);
> return;
> }
>
> @@ -1010,15 +1010,15 @@ fs_visitor::swizzle_result(ir_texture_opcode op, int
> dest_components,
> for (int i = 0; i < 4; i++) {
> int swiz = GET_SWZ(key_tex->swizzles[sampler], i);
> fs_reg l = swizzled_result;
> - l = offset(l, i);
> + l = bld.offset(l, i);
>
> if (swiz == SWIZZLE_ZERO) {
> bld.MOV(l, fs_reg(0.0f));
> } else if (swiz == SWIZZLE_ONE) {
> bld.MOV(l, fs_reg(1.0f));
> } else {
> - bld.MOV(l, offset(orig_val,
> - GET_SWZ(key_tex->swizzles[sampler], i)));
> + bld.MOV(l, bld.offset(orig_val,
> + GET_SWZ(key_tex->swizzles[sampler], i)));
> }
> }
> this->result = swizzled_result;
> @@ -1315,14 +1315,14 @@ fs_visitor::emit_interpolation_setup_gen4()
>
> if (devinfo->has_pln && dispatch_width == 16) {
> for (unsigned i = 0; i < 2; i++) {
> - abld.half(i).ADD(half(offset(delta_xy, i), 0),
> - half(this->pixel_x, i), xstart);
> - abld.half(i).ADD(half(offset(delta_xy, i), 1),
> - half(this->pixel_y, i), ystart);
> + abld.half(i).ADD(abld.half(abld.offset(delta_xy, i), 0),
> + abld.half(this->pixel_x, i), xstart);
> + abld.half(i).ADD(abld.half(abld.offset(delta_xy, i), 1),
> + abld.half(this->pixel_y, i), ystart);
> }
> } else {
> - abld.ADD(offset(delta_xy, 0), this->pixel_x, xstart);
> - abld.ADD(offset(delta_xy, 1), this->pixel_y, ystart);
> + abld.ADD(abld.offset(delta_xy, 0), this->pixel_x, xstart);
> + abld.ADD(abld.offset(delta_xy, 1), this->pixel_y, ystart);
> }
>
> abld = bld.annotate("compute pos.w and 1/pos.w");
> @@ -1419,7 +1419,7 @@ fs_visitor::setup_color_payload(fs_reg *dst, fs_reg
> color, unsigned components,
> fs_reg tmp = vgrf(glsl_type::vec4_type);
> assert(color.type == BRW_REGISTER_TYPE_F);
> for (unsigned i = 0; i < components; i++) {
> - inst = bld.MOV(offset(tmp, i), offset(color, i));
> + inst = bld.MOV(bld.offset(tmp, i), bld.offset(color, i));
> inst->saturate = true;
> }
> color = tmp;
> @@ -1428,10 +1428,10 @@ fs_visitor::setup_color_payload(fs_reg *dst, fs_reg
> color, unsigned components,
> if (exec_size < dispatch_width) {
> unsigned half_idx = use_2nd_half ? 1 : 0;
> for (unsigned i = 0; i < components; i++)
> - dst[i] = half(offset(color, i), half_idx);
> + dst[i] = bld.half(bld.offset(color, i), half_idx);
> } else {
> for (unsigned i = 0; i < components; i++)
> - dst[i] = offset(color, i);
> + dst[i] = bld.offset(color, i);
> }
> }
>
> @@ -1479,7 +1479,7 @@ fs_visitor::emit_alpha_test()
> BRW_CONDITIONAL_NEQ);
> } else {
> /* RT0 alpha */
> - fs_reg color = offset(outputs[0], 3);
> + fs_reg color = bld.offset(outputs[0], 3);
>
> /* f0.1 &= func(color, ref) */
> cmp = abld.CMP(bld.null_reg_f(), color, fs_reg(key->alpha_test_ref),
> @@ -1556,7 +1556,8 @@ fs_visitor::emit_single_fb_write(const fs_builder &bld,
> * alpha-testing, alpha-to-coverage, and so on.
> */
> if (this->outputs[0].file != BAD_FILE)
> - setup_color_payload(&sources[length + 3], offset(this->outputs[0],
> 3),
> + setup_color_payload(&sources[length + 3],
> + bld.offset(this->outputs[0], 3),
> 1, exec_size, false);
> length += 4;
> } else if (color1.file == BAD_FILE) {
> @@ -1591,7 +1592,7 @@ fs_visitor::emit_single_fb_write(const fs_builder &bld,
> /* Hand over gl_FragDepth. */
> assert(this->frag_depth.file != BAD_FILE);
> if (exec_size < dispatch_width) {
> - sources[length] = half(this->frag_depth, use_2nd_half);
> + sources[length] = bld.half(this->frag_depth, use_2nd_half);
> } else {
> sources[length] = this->frag_depth;
> }
> @@ -1692,7 +1693,7 @@ fs_visitor::emit_fb_writes()
>
> fs_reg src0_alpha;
> if (devinfo->gen >= 6 && key->replicate_alpha && target != 0)
> - src0_alpha = offset(outputs[0], 3);
> + src0_alpha = bld.offset(outputs[0], 3);
>
> inst = emit_single_fb_write(abld, this->outputs[target], reg_undef,
> src0_alpha,
> @@ -1776,7 +1777,7 @@ void fs_visitor::compute_clip_distance()
> abld.MUL(output, outputs[clip_vertex], u);
> for (int j = 1; j < 4; j++) {
> u.reg = userplane[i].reg + j;
> - abld.MAD(output, output, offset(outputs[clip_vertex], j), u);
> + abld.MAD(output, output, bld.offset(outputs[clip_vertex], j), u);
> }
> }
> }
> @@ -1890,13 +1891,13 @@ fs_visitor::emit_urb_writes()
> */
> for (int i = 0; i < 4; i++) {
> reg = fs_reg(GRF, alloc.allocate(1), outputs[varying].type);
> - src = offset(this->outputs[varying], i);
> + src = bld.offset(this->outputs[varying], i);
> set_saturate(true, bld.MOV(reg, src));
> sources[length++] = reg;
> }
> } else {
> for (int i = 0; i < 4; i++)
> - sources[length++] = offset(this->outputs[varying], i);
> + sources[length++] = bld.offset(this->outputs[varying], i);
> }
> break;
> }
> diff --git a/src/mesa/drivers/dri/i965/brw_ir_fs.h
> b/src/mesa/drivers/dri/i965/brw_ir_fs.h
> index 96dc20d..10033ca 100644
> --- a/src/mesa/drivers/dri/i965/brw_ir_fs.h
> +++ b/src/mesa/drivers/dri/i965/brw_ir_fs.h
> @@ -129,27 +129,6 @@ horiz_offset(fs_reg reg, unsigned delta)
> }
>
> static inline fs_reg
> -offset(fs_reg reg, unsigned delta)
> -{
> - switch (reg.file) {
> - case BAD_FILE:
> - break;
> - case GRF:
> - case MRF:
> - case ATTR:
> - return byte_offset(reg,
> - delta * MAX2(reg.width * reg.stride, 1) *
> - type_sz(reg.type));
> - case UNIFORM:
> - reg.reg_offset += delta;
> - break;
> - default:
> - assert(delta == 0);
> - }
> - return reg;
> -}
> -
> -static inline fs_reg
> component(fs_reg reg, unsigned idx)
> {
> assert(reg.subreg_offset == 0);
> @@ -167,36 +146,6 @@ is_uniform(const fs_reg ®)
> (!reg.reladdr || is_uniform(*reg.reladdr));
> }
>
> -/**
> - * Get either of the 8-component halves of a 16-component register.
> - *
> - * Note: this also works if \c reg represents a SIMD16 pair of registers.
> - */
> -static inline fs_reg
> -half(fs_reg reg, unsigned idx)
> -{
> - assert(idx < 2);
> -
> - switch (reg.file) {
> - case BAD_FILE:
> - case UNIFORM:
> - case IMM:
> - return reg;
> -
> - case GRF:
> - case MRF:
> - assert(reg.width == 16);
> - reg.width = 8;
> - return horiz_offset(reg, 8 * idx);
> -
> - case ATTR:
> - case HW_REG:
> - default:
> - unreachable("Cannot take half of this register type");
> - }
> - return reg;
> -}
> -
> static const fs_reg reg_undef;
>
> class fs_inst : public backend_instruction {
> --
> 2.4.3
>
> _______________________________________________
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> mesa-dev@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/mesa-dev
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