On Tuesday, June 16, 2015 02:46:22 PM Jordan Justen wrote: > Although we don't support SIMD32, krh pointed out that the left shift > by 32 is undefined by C/C++ for 32-bit integers. > > Suggested-by: Kristian Høgsberg <k...@bitplanet.net> > Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> > Cc: Kristian Høgsberg <k...@bitplanet.net> > --- > src/mesa/drivers/dri/i965/brw_compute.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/src/mesa/drivers/dri/i965/brw_compute.c > b/src/mesa/drivers/dri/i965/brw_compute.c > index b3d6de5..5693ab5 100644 > --- a/src/mesa/drivers/dri/i965/brw_compute.c > +++ b/src/mesa/drivers/dri/i965/brw_compute.c > @@ -45,7 +45,7 @@ brw_emit_gpgpu_walker(struct brw_context *brw, const GLuint > *num_groups) > unsigned thread_width_max = > (group_size + simd_size - 1) / simd_size; > > - uint32_t right_mask = (1u << simd_size) - 1; > + uint32_t right_mask = 0xffffffffu >> (32 - simd_size); > const unsigned right_non_aligned = group_size & (simd_size - 1); > if (right_non_aligned != 0) > right_mask >>= (simd_size - right_non_aligned); >
Patch works as advertised: python>> hex((1 << 8) - 1) '0xff' python>> hex((1 << 16) - 1) '0xffff' python>> hex((1 << 32) - 1) '0xffffffff' python>> hex(0xffffffff >> (32 - 8)) '0xff' python>> hex(0xffffffff >> (32 - 16)) '0xffff' python>> hex(0xffffffff >> (32 - 32)) '0xffffffff' Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
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