Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
Cc: Ben Widawsky <b...@bwidawsk.net>
---
Jenkins showed no piglit regressions with this series.
src/mesa/drivers/dri/i965/brw_tex_layout.c | 20 +++++++++++++-------
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 41a9964..b9ac4cf 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -761,16 +761,12 @@ intel_miptree_set_total_width_height(struct brw_context
*brw,
mt->total_width, mt->total_height, mt->cpp);
}
-void
-brw_miptree_layout(struct brw_context *brw,
- bool for_bo,
- enum intel_miptree_tiling_mode requested,
- struct intel_mipmap_tree *mt)
+static void
+intel_miptree_set_alignment(struct brw_context *brw,
+ struct intel_mipmap_tree *mt)
{
bool gen6_hiz_or_stencil = false;
- mt->tr_mode = INTEL_MIPTREE_TRMODE_NONE;
-
if (brw->gen == 6 && mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
const GLenum base_format = _mesa_get_format_base_format(mt->format);
gen6_hiz_or_stencil = _mesa_is_depth_or_stencil_format(base_format);
@@ -803,7 +799,17 @@ brw_miptree_layout(struct brw_context *brw,
mt->align_w = intel_horizontal_texture_alignment_unit(brw, mt);
mt->align_h = intel_vertical_texture_alignment_unit(brw, mt);
}
+}
+
+void
+brw_miptree_layout(struct brw_context *brw,
+ bool for_bo,
+ enum intel_miptree_tiling_mode requested,
+ struct intel_mipmap_tree *mt)
+{
+ mt->tr_mode = INTEL_MIPTREE_TRMODE_NONE;
+ intel_miptree_set_alignment(brw, mt);
intel_miptree_set_total_width_height(brw, mt);
if (!mt->total_width || !mt->total_height) {
--
1.9.3
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