On Sun, Jun 07, 2015 at 01:01:48AM -0700, Kenneth Graunke wrote:
> On Friday, June 05, 2015 03:14:29 PM Chris Wilson wrote:
> > The BLT pitch is specified in bytes for linear surfaces and in dwords
> > for tiled surfaces. In both cases the programmable limit is 32,767, so
> > adjust the check to compensate for the effect of tiling.
> >
> > Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
> > Cc: Kristian Høgsberg <k...@bitplanet.net>
> > Cc: Kenneth Graunke <kenn...@whitecape.org>
> > ---
> > src/mesa/drivers/dri/i965/intel_blit.c | 18 +++++++++++++-----
> > 1 file changed, 13 insertions(+), 5 deletions(-)
> >
> > diff --git a/src/mesa/drivers/dri/i965/intel_blit.c
> > b/src/mesa/drivers/dri/i965/intel_blit.c
> > index 7680a40..360bfe8 100644
> > --- a/src/mesa/drivers/dri/i965/intel_blit.c
> > +++ b/src/mesa/drivers/dri/i965/intel_blit.c
> > @@ -130,6 +130,14 @@ set_blitter_tiling(struct brw_context *brw,
> > ADVANCE_BATCH(); \
> > } while (0)
> >
> > +static int blt_pitch(struct intel_mipmap_tree *mt)
>
> static int
> blt_pitch(struct intel_mipmap_tree *mt)
>
> > +{
> > + int pitch = mt->pitch;
> > + if (mt->tiling)
> > + pitch /= 4;
> > + return pitch;
> > +}
>
> Wow, the docs are really confusing. They sure make it sound like the
> XY_SRC_COPY_BLT pitch is *always* specified in DWords, even for linear
> buffers.
Indeed, they have been badly mangled over the years. The early gen4 docs
are reasonably clear here at least. I never understood why they didn't
use a larger pitch unit (since it has to be tile width aligned) so that
the BLT unit could match the sampler in terms of maximum supported pitch.
> But, our existing code is definitely only dividing by 4 for tiled surfaces,
> and has been doing that for years...
When in doubt, do as the hw does :)
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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