On 2015-05-28 10:21:31, Ben Widawsky wrote:
> There are several constraints when determining if one can fast clear a
> surface.
> Some of these are alignment, pixel density, tiling formats, and others that
> vary
> by generation. The helper function which exists today does a suitable job,
> however it conflates "BO properties" with "Miptree properties" when using
> tiling. I consider the former to be attributes of the physical surface, things
> which are determined through BO allocation, and the latter being attributes
> which are derived from the API, and having nothing to do with the underlying
> surface.
>
> Tiling properties are a distinct operation from the creation of a miptree, and
> by removing this, we gain flexibility throughout the code to make
> determinations
> about when we can or cannot fast clear strictly on the miptree.
>
> To signify this change, I've also renamed the function to indicate it is a
> distinction made on the miptree. I am torn as to whether or not it was a good
> idea to remove "non_msrt" since it's a really nice thing for grep.
>
> Cc: Chad Versace <chad.vers...@linux.intel.com>
> Signed-off-by: Ben Widawsky <b...@bwidawsk.net>
> ---
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 37
> +++++++++++++++++++--------
> src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 11 ++++----
> 2 files changed, 32 insertions(+), 16 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index 68d405c..75ee19a 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -158,15 +158,33 @@ intel_get_non_msrt_mcs_alignment(struct brw_context
> *brw,
> }
> }
>
> +/**
> + * Determine the BO backing the miptree has a suitable tile format. For Gen7,
"Determine if" ...
I kind of thought patch 2 & 3 could be swapped, but it doesn't seem
too important.
1-3 Reviewed-by: Jordan Justen <jordan.l.jus...@intel.com>
> + * and 8 this means any tiled format.
> + *
> + * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
> Target(s)",
> + * beneath the "Fast Color Clear" bullet (p326):
> + *
> + * - Support is limited to tiled render targets.
> + */
> +bool
> +intel_is_non_msrt_mcs_tile_supported(struct brw_context *brw,
> + unsigned tiling)
> +{
> + if (brw->gen >= 9)
> + return tiling == I915_TILING_Y;
> +
> + return tiling != I915_TILING_NONE;
> +}
>
> /**
> * For a single-sampled render target ("non-MSRT"), determine if an MCS
> buffer
> - * can be used.
> + * can be used. This doesn't (and should not) inquire about the BO
> properties of
> + * the buffer.
> *
> * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
> Target(s)",
> * beneath the "Fast Color Clear" bullet (p326):
> *
> - * - Support is limited to tiled render targets.
> * - Support is for non-mip-mapped and non-array surface types only.
> *
> * And then later, on p327:
> @@ -175,8 +193,8 @@ intel_get_non_msrt_mcs_alignment(struct brw_context *brw,
> * 64bpp, and 128bpp.
> */
> bool
> -intel_is_non_msrt_mcs_buffer_supported(struct brw_context *brw,
> - struct intel_mipmap_tree *mt)
> +intel_miptree_is_fast_clear_capable(struct brw_context *brw,
> + struct intel_mipmap_tree *mt)
> {
> /* MCS support does not exist prior to Gen7 */
> if (brw->gen < 7)
> @@ -193,11 +211,6 @@ intel_is_non_msrt_mcs_buffer_supported(struct
> brw_context *brw,
> return false;
> }
>
> - if (brw->gen >= 9 && mt->tiling != I915_TILING_Y)
> - return false;
> - if (mt->tiling != I915_TILING_X &&
> - mt->tiling != I915_TILING_Y)
> - return false;
> if (mt->cpp != 4 && mt->cpp != 8 && mt->cpp != 16)
> return false;
> if (mt->first_level != 0 || mt->last_level != 0)
> @@ -720,7 +733,8 @@ intel_miptree_create(struct brw_context *brw,
> * Allocation of the MCS miptree will be deferred until the first fast
> * clear actually occurs.
> */
> - if (intel_is_non_msrt_mcs_buffer_supported(brw, mt))
> + if (intel_is_non_msrt_mcs_tile_supported(brw, mt->tiling) &&
> + intel_miptree_is_fast_clear_capable(brw, mt))
> mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED;
>
> return mt;
> @@ -819,7 +833,8 @@ intel_update_winsys_renderbuffer_miptree(struct
> brw_context *intel,
> * Allocation of the MCS miptree will be deferred until the first fast
> * clear actually occurs.
> */
> - if (intel_is_non_msrt_mcs_buffer_supported(intel, singlesample_mt))
> + if (intel_is_non_msrt_mcs_tile_supported(intel, singlesample_mt->tiling)
> &&
> + intel_miptree_is_fast_clear_capable(intel, singlesample_mt))
> singlesample_mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED;
>
> if (num_samples == 0) {
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> index 4722353..ccb6d72 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> @@ -514,15 +514,16 @@ enum intel_miptree_tiling_mode {
> INTEL_MIPTREE_TILING_NONE,
> };
>
> -bool
> -intel_is_non_msrt_mcs_buffer_supported(struct brw_context *brw,
> - struct intel_mipmap_tree *mt);
> -
> void
> intel_get_non_msrt_mcs_alignment(struct brw_context *brw,
> struct intel_mipmap_tree *mt,
> unsigned *width_px, unsigned *height);
> -
> +bool
> +intel_is_non_msrt_mcs_tile_supported(struct brw_context *brw,
> + unsigned tiling);
> +bool
> +intel_miptree_is_fast_clear_capable(struct brw_context *brw,
> + struct intel_mipmap_tree *mt);
> bool
> intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
> struct intel_mipmap_tree *mt);
> --
> 2.4.2
>
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