Hello list,
The candidate for the Mesa 10.5.5 is now available. The current patch queue
is as follows:
- 10 queued
- 5 nominated (outstanding)
- and 0 rejected (obsolete) patches
The queue consists mostly of nouveau and i965 fixes.
Take a look at section "Mesa stable queue" for more information.
Testing
-------
The following results are against piglit 305ecc3ac89.
Changes - classic i965(snb)
---------------------------
None.
Changes - swrast classic
------------------------
None.
Changes - gallium softpipe
--------------------------
None.
Fixes:
- spec
+ arb_texture_buffer_object
+ formats (vs, 3.1 core)
+ GL_RG32F fail > pass
Changes - gallium llvmpipe (LLVM 3.6)
-------------------------------------
None.
Testing reports/general approval
--------------------------------
Any testing reports (or general approval of the state of the branch)
will be greatly appreciated.
Trivial merge conflicts
-----------------------
None.
The plan is to have 10.5.5 this Friday(8th of May).
If you have any questions or comments that you would like to share
before the release, please go ahead.
Cheers,
Emil
Mesa stable queue
-----------------
Nominated (5)
=============
Alejandro Piñeiro (1):
glsl: properly setting var->data.binding if explicit_binding is true
Boyan Ding (1):
i915: Add XRGB8888 format to intel_screen_make_configs
Brian Paul (1):
configure: don't try to build gallium DRI drivers if --disable-dri is set
Roland Scheidegger (1):
draw: (trivial) fix out-of-bounds vector initialization
Tom Stellard (1):
clover: Update the wait_count of the correct event when chaining events
Queued (10)
===========
Boyan Ding (1):
i965: Add XRGB8888 format to intel_screen_make_configs
Emil Velikov (2):
docs: Add sha256 sums for the 10.5.4 release
r300: do not link against libdrm_intel
Ilia Mirkin (4):
nvc0/ir: flush denorms to zero in non-compute shaders
gk110/ir: fix set with a register dest to not auto-set the abs flag
nvc0/ir: fix predicated PFETCH emission
nv50/ir: fix asFlow() const helper for OP_JOIN
Kenneth Graunke (2):
i965: Make intel_emit_linear_blit handle Gen8+ alignment restrictions.
i965: Disallow linear blits that are not cacheline aligned.
Roland Scheidegger (1):
draw: fix prim ids when there's no gs
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
