---
src/mesa/drivers/dri/i965/brw_fs.h | 7 --
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 12 ++-
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 125 ++-------------------------
3 files changed, 10 insertions(+), 134 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index 3b9907e..a0bba8d 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -411,13 +411,6 @@ public:
void emit_shader_time_end();
fs_inst *SHADER_TIME_ADD(enum shader_time_shader_type type, fs_reg value);
- void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
- fs_reg dst, fs_reg offset, fs_reg src0,
- fs_reg src1);
-
- void emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
- fs_reg offset);
-
void emit_interpolate_expression(ir_expression *ir);
bool try_rewrite_rhs_to_dst(ir_assignment *ir,
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 1443ef0..6ae130a 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -1311,19 +1311,17 @@ fs_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr)
/* Emit a surface read or atomic op. */
switch (instr->intrinsic) {
case nir_intrinsic_atomic_counter_read:
- tmp = surface_access::emit_untyped_read(bld, surface, offset, 1, 1);
+ tmp = emit_untyped_read(bld, surface, offset, 1, 1);
break;
case nir_intrinsic_atomic_counter_inc:
- tmp = surface_access::emit_untyped_atomic(
- bld, surface, offset, fs_reg(),
- fs_reg(), 1, rsize, BRW_AOP_INC);
+ tmp = emit_untyped_atomic(bld, surface, offset, fs_reg(),
+ fs_reg(), 1, rsize, BRW_AOP_INC);
break;
case nir_intrinsic_atomic_counter_dec:
- tmp = surface_access::emit_untyped_atomic(
- bld, surface, offset, fs_reg(),
- fs_reg(), 1, rsize, BRW_AOP_PREDEC);
+ tmp = emit_untyped_atomic(bld, surface, offset, fs_reg(),
+ fs_reg(), 1, rsize, BRW_AOP_PREDEC);
break;
default:
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 82b9c6e..4cb05b8 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -3200,17 +3200,15 @@ fs_visitor::visit_atomic_counter_intrinsic(const
fs_builder &bld, ir_call *ir)
/* Emit a surface read or atomic op. */
if (!strcmp("__intrinsic_atomic_read", callee))
- tmp = surface_access::emit_untyped_read(bld, surface, offset, 1, 1);
+ tmp = emit_untyped_read(bld, surface, offset, 1, 1);
else if (!strcmp("__intrinsic_atomic_increment", callee))
- tmp = surface_access::emit_untyped_atomic(
- bld, surface, offset, fs_reg(), fs_reg(),
- 1, rsize, BRW_AOP_INC);
+ tmp = emit_untyped_atomic(bld, surface, offset, fs_reg(), fs_reg(),
+ 1, rsize, BRW_AOP_INC);
else if (!strcmp("__intrinsic_atomic_predecrement", callee))
- tmp = surface_access::emit_untyped_atomic(
- bld, surface, offset, fs_reg(), fs_reg(),
- 1, rsize, BRW_AOP_PREDEC);
+ tmp = emit_untyped_atomic(bld, surface, offset, fs_reg(), fs_reg(),
+ 1, rsize, BRW_AOP_PREDEC);
/* Assign the result. */
if (ir->return_deref)
@@ -3435,119 +3433,6 @@ fs_visitor::visit(ir_end_primitive *)
unreachable("not reached");
}
-void
-fs_visitor::emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
- fs_reg dst, fs_reg offset, fs_reg src0,
- fs_reg src1)
-{
- int reg_width = dispatch_width / 8;
- int length = 0;
-
- fs_reg *sources = ralloc_array(mem_ctx, fs_reg, 4);
-
- sources[0] = fs_reg(GRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
- /* Initialize the sample mask in the message header. */
- emit(MOV(sources[0], fs_reg(0u)))
- ->force_writemask_all = true;
-
- if (stage == MESA_SHADER_FRAGMENT) {
- if (((brw_wm_prog_data*)this->prog_data)->uses_kill) {
- emit(MOV(component(sources[0], 7), brw_flag_reg(0, 1)))
- ->force_writemask_all = true;
- } else {
- emit(MOV(component(sources[0], 7),
- retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD)))
- ->force_writemask_all = true;
- }
- } else {
- /* The execution mask is part of the side-band information sent together
with
- * the message payload to the data port. It's implicitly ANDed with the
sample
- * mask sent in the header to compute the actual set of channels that
execute
- * the atomic operation.
- */
- assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_COMPUTE);
- emit(MOV(component(sources[0], 7),
- fs_reg(0xffffu)))->force_writemask_all = true;
- }
- length++;
-
- /* Set the atomic operation offset. */
- sources[1] = vgrf(glsl_type::uint_type);
- emit(MOV(sources[1], offset));
- length++;
-
- /* Set the atomic operation arguments. */
- if (src0.file != BAD_FILE) {
- sources[length] = vgrf(glsl_type::uint_type);
- emit(MOV(sources[length], src0));
- length++;
- }
-
- if (src1.file != BAD_FILE) {
- sources[length] = vgrf(glsl_type::uint_type);
- emit(MOV(sources[length], src1));
- length++;
- }
-
- int mlen = 1 + (length - 1) * reg_width;
- fs_reg src_payload = fs_reg(GRF, alloc.allocate(mlen),
- BRW_REGISTER_TYPE_UD);
- emit(LOAD_PAYLOAD(src_payload, sources, length));
-
- /* Emit the instruction. */
- fs_inst *inst = emit(SHADER_OPCODE_UNTYPED_ATOMIC, dst, src_payload,
- fs_reg(surf_index), fs_reg(atomic_op));
- inst->mlen = mlen;
-}
-
-void
-fs_visitor::emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
- fs_reg offset)
-{
- int reg_width = dispatch_width / 8;
-
- fs_reg *sources = ralloc_array(mem_ctx, fs_reg, 2);
-
- sources[0] = fs_reg(GRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
- /* Initialize the sample mask in the message header. */
- emit(MOV(sources[0], fs_reg(0u)))
- ->force_writemask_all = true;
-
- if (stage == MESA_SHADER_FRAGMENT) {
- if (((brw_wm_prog_data*)this->prog_data)->uses_kill) {
- emit(MOV(component(sources[0], 7), brw_flag_reg(0, 1)))
- ->force_writemask_all = true;
- } else {
- emit(MOV(component(sources[0], 7),
- retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD)))
- ->force_writemask_all = true;
- }
- } else {
- /* The execution mask is part of the side-band information sent together
with
- * the message payload to the data port. It's implicitly ANDed with the
sample
- * mask sent in the header to compute the actual set of channels that
execute
- * the atomic operation.
- */
- assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_COMPUTE);
- emit(MOV(component(sources[0], 7),
- fs_reg(0xffffu)))->force_writemask_all = true;
- }
-
- /* Set the surface read offset. */
- sources[1] = vgrf(glsl_type::uint_type);
- emit(MOV(sources[1], offset));
-
- int mlen = 1 + reg_width;
- fs_reg src_payload = fs_reg(GRF, alloc.allocate(mlen),
- BRW_REGISTER_TYPE_UD);
- fs_inst *inst = emit(LOAD_PAYLOAD(src_payload, sources, 2));
-
- /* Emit the instruction. */
- inst = emit(SHADER_OPCODE_UNTYPED_SURFACE_READ, dst, src_payload,
- fs_reg(surf_index), fs_reg(1));
- inst->mlen = mlen;
-}
-
fs_inst *
fs_visitor::emit(fs_inst *inst)
{
--
2.3.5
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