---
src/mesa/drivers/dri/i965/brw_fs.cpp | 25 ++++++++++++--------
src/mesa/drivers/dri/i965/brw_shader.cpp | 32 ++++++++++++++++++++++++++
src/mesa/drivers/dri/i965/brw_shader.h | 2 ++
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 23 +++++++++++++-----
4 files changed, 66 insertions(+), 16 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 1805db2..4340170 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -680,6 +680,7 @@ fs_visitor::type_size(const struct glsl_type *type)
case GLSL_TYPE_ATOMIC_UINT:
return 0;
case GLSL_TYPE_IMAGE:
+ return BRW_IMAGE_PARAM_SIZE;
case GLSL_TYPE_VOID:
case GLSL_TYPE_ERROR:
case GLSL_TYPE_INTERFACE:
@@ -1205,7 +1206,6 @@ fs_visitor::setup_uniform_values(ir_variable *ir)
* order we'd walk the type, so walk the list of storage and find anything
* with our name, or the prefix of a component that starts with our name.
*/
- unsigned params_before = uniforms;
for (unsigned u = 0; u < shader_prog->NumUserUniformStorage; u++) {
struct gl_uniform_storage *storage = &shader_prog->UniformStorage[u];
@@ -1216,18 +1216,23 @@ fs_visitor::setup_uniform_values(ir_variable *ir)
continue;
}
- unsigned slots = storage->type->component_slots();
- if (storage->array_elements)
- slots *= storage->array_elements;
+ if (storage->type->is_image()) {
+ const struct brw_image_param *image_params =
+ (stage == MESA_SHADER_FRAGMENT ? brw->wm.base.image_params :
+ stage == MESA_SHADER_VERTEX ? brw->vs.base.image_params : NULL);
+ assert(image_params);
- for (unsigned i = 0; i < slots; i++) {
- stage_prog_data->param[uniforms++] = &storage->storage[i];
+ setup_image_uniform_values(storage, image_params);
+
+ } else {
+ unsigned slots = storage->type->component_slots();
+ if (storage->array_elements)
+ slots *= storage->array_elements;
+
+ for (unsigned i = 0; i < slots; i++)
+ stage_prog_data->param[uniforms++] = &storage->storage[i];
}
}
-
- /* Make sure we actually initialized the right amount of stuff here. */
- assert(params_before + ir->type->component_slots() == uniforms);
- (void)params_before;
}
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index c1fd859..61ef0c0 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -1260,3 +1260,35 @@
backend_visitor::assign_common_binding_table_offsets(uint32_t next_binding_table
/* prog_data->base.binding_table.size will be set by brw_mark_surface_used.
*/
}
+
+void
+backend_visitor::setup_image_uniform_values(
+ const gl_uniform_storage *storage, const brw_image_param *image_params)
+{
+ const unsigned stage = _mesa_program_enum_to_shader_stage(prog->Target);
+
+ for (unsigned i = 0; i < MAX2(storage->array_elements, 1); i++) {
+ const unsigned image_idx = storage->image[stage].index + i;
+ const brw_image_param *param = &image_params[image_idx];
+
+ /* Upload the brw_image_param structure. The order is expected to match
+ * the BRW_IMAGE_PARAM_*_OFFSET defines.
+ */
+ setup_vector_uniform_values(
+ (const gl_constant_value *)¶m->surface_idx, 1);
+ setup_vector_uniform_values(
+ (const gl_constant_value *)param->offset, 2);
+ setup_vector_uniform_values(
+ (const gl_constant_value *)param->size, 3);
+ setup_vector_uniform_values(
+ (const gl_constant_value *)param->stride, 4);
+ setup_vector_uniform_values(
+ (const gl_constant_value *)param->tiling, 3);
+ setup_vector_uniform_values(
+ (const gl_constant_value *)param->swizzling, 2);
+
+ brw_mark_surface_used(
+ stage_prog_data,
+ stage_prog_data->binding_table.image_start + image_idx);
+ }
+}
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h
b/src/mesa/drivers/dri/i965/brw_shader.h
index 6aa7e09..f5f4517 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -261,6 +261,8 @@ public:
virtual void setup_vector_uniform_values(const gl_constant_value *values,
unsigned n) = 0;
+ void setup_image_uniform_values(const gl_uniform_storage *storage,
+ const struct brw_image_param *image_params);
};
uint32_t brw_texture_offset(int *offsets, unsigned num_components);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 4fbb158..988886f 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -611,6 +611,7 @@ type_size(const struct glsl_type *type)
case GLSL_TYPE_ATOMIC_UINT:
return 0;
case GLSL_TYPE_IMAGE:
+ return BRW_IMAGE_PARAM_SIZE / 4;
case GLSL_TYPE_VOID:
case GLSL_TYPE_DOUBLE:
case GLSL_TYPE_ERROR:
@@ -708,13 +709,23 @@ vec4_visitor::setup_uniform_values(ir_variable *ir)
continue;
}
- const unsigned vector_count = (MAX2(storage->array_elements, 1) *
- storage->type->matrix_columns);
- const unsigned vector_size = storage->type->vector_elements;
+ if (storage->type->is_image()) {
+ const brw_image_param *image_params =
+ (stage == MESA_SHADER_VERTEX ? brw->vs.base.image_params :
+ stage == MESA_SHADER_GEOMETRY ? brw->gs.base.image_params : NULL);
+ assert(image_params);
- for (unsigned s = 0; s < vector_count; s++)
- setup_vector_uniform_values(&storage->storage[s * vector_size],
- vector_size);
+ setup_image_uniform_values(storage, image_params);
+
+ } else {
+ const unsigned vector_count = (MAX2(storage->array_elements, 1) *
+ storage->type->matrix_columns);
+ const unsigned vector_size = storage->type->vector_elements;
+
+ for (unsigned s = 0; s < vector_count; s++)
+ setup_vector_uniform_values(&storage->storage[s * vector_size],
+ vector_size);
+ }
}
}
--
2.3.5
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