On Fri, Apr 17, 2015 at 04:51:33PM -0700, Anuj Phogat wrote:
> This function will be utilised in later patches.
>
> Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
> ---
> src/mesa/drivers/dri/i965/brw_context.h | 4 ++++
> src/mesa/drivers/dri/i965/brw_tex_layout.c | 10 +++++-----
> 2 files changed, 9 insertions(+), 5 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_context.h
> b/src/mesa/drivers/dri/i965/brw_context.h
> index 6c168a3..3d0b35c 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.h
> +++ b/src/mesa/drivers/dri/i965/brw_context.h
> @@ -1938,6 +1938,10 @@ gen6_upload_push_constants(struct brw_context *brw,
> struct brw_stage_state *stage_state,
> enum aub_state_struct_type type);
>
> +bool
> +gen9_use_linear_1d_layout(struct brw_context *brw,
> + struct intel_mipmap_tree *mt);
I would use the opportunity to make both pointers constants - the function
only uses them for reading. Anyway:
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
> +
> #ifdef __cplusplus
> }
> #endif
> diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
> b/src/mesa/drivers/dri/i965/brw_tex_layout.c
> index 9342101..28927e9 100644
> --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
> +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
> @@ -430,9 +430,9 @@ align_cube(struct intel_mipmap_tree *mt)
> mt->total_height += 2;
> }
>
> -static bool
> -use_linear_1d_layout(struct brw_context *brw,
> - struct intel_mipmap_tree *mt)
> +bool
> +gen9_use_linear_1d_layout(struct brw_context *brw,
> + struct intel_mipmap_tree *mt)
> {
> /* On Gen9+ the mipmap levels of a 1D surface are all laid out in a
> * horizontal line. This isn't done for depth/stencil buffers however
> @@ -458,7 +458,7 @@ brw_miptree_layout_texture_array(struct brw_context *brw,
> {
> int h0, h1;
> unsigned height = mt->physical_height0;
> - bool layout_1d = use_linear_1d_layout(brw, mt);
> + bool layout_1d = gen9_use_linear_1d_layout(brw, mt);
>
> h0 = ALIGN(mt->physical_height0, mt->align_h);
> h1 = ALIGN(minify(mt->physical_height0, 1), mt->align_h);
> @@ -674,7 +674,7 @@ intel_miptree_total_width_height(struct brw_context *brw,
> break;
> case INTEL_MSAA_LAYOUT_NONE:
> case INTEL_MSAA_LAYOUT_IMS:
> - if (use_linear_1d_layout(brw, mt))
> + if (gen9_use_linear_1d_layout(brw, mt))
> gen9_miptree_layout_1d(mt);
> else
> brw_miptree_layout_2d(mt);
> --
> 2.3.4
>
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