On Fri, Apr 17, 2015 at 04:51:32PM -0700, Anuj Phogat wrote:
> This patch sets the tiled resource mode for texture and renderbuffer
> surfaces.
>
> Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
> ---
> src/mesa/drivers/dri/i965/brw_defines.h | 6 ++++++
> src/mesa/drivers/dri/i965/gen8_surface_state.c | 22 ++++++++++++++++++++++
> 2 files changed, 28 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
> b/src/mesa/drivers/dri/i965/brw_defines.h
> index da6ed5b..c62c09b 100644
> --- a/src/mesa/drivers/dri/i965/brw_defines.h
> +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> @@ -588,6 +588,12 @@
> #define GEN7_SURFACE_MOCS_SHIFT 16
> #define GEN7_SURFACE_MOCS_MASK INTEL_MASK(19, 16)
>
> +#define GEN9_SURFACE_TRMODE_SHIFT 18
> +#define GEN9_SURFACE_TRMODE_MASK INTEL_MASK(19, 18)
> +#define GEN9_SURFACE_TRMODE_NONE 0
> +#define GEN9_SURFACE_TRMODE_TILEYF 1
> +#define GEN9_SURFACE_TRMODE_TILEYS 2
> +
> /* Surface state DW6 */
> #define GEN7_SURFACE_MCS_ENABLE (1 << 0)
> #define GEN7_SURFACE_MCS_PITCH_SHIFT 3
> diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c
> b/src/mesa/drivers/dri/i965/gen8_surface_state.c
> index 7f82f53..d2eceff 100644
> --- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
> +++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
> @@ -56,6 +56,19 @@ swizzle_to_scs(unsigned swizzle)
> }
>
> static uint32_t
> +surface_tiling_resource_mode(uint32_t tr_mode)
> +{
> + switch (tr_mode) {
> + case INTEL_MIPTREE_TRMODE_YF:
> + return GEN9_SURFACE_TRMODE_TILEYF;
> + case INTEL_MIPTREE_TRMODE_YS:
> + return GEN9_SURFACE_TRMODE_TILEYS;
> + default:
> + return GEN9_SURFACE_TRMODE_NONE;
> + }
> +}
> +
> +static uint32_t
> surface_tiling_mode(uint32_t tiling)
> {
> switch (tiling) {
> @@ -173,6 +186,8 @@ gen8_update_texture_surface(struct gl_context *ctx,
> }
>
> unsigned tiling_mode, pitch;
> + unsigned tr_mode = surface_tiling_resource_mode(mt->tr_mode);
> +
> if (format == MESA_FORMAT_S_UINT8) {
> tiling_mode = GEN8_SURFACE_TILING_W;
> pitch = 2 * mt->pitch;
> @@ -227,6 +242,9 @@ gen8_update_texture_surface(struct gl_context *ctx,
> GEN7_SURFACE_MIN_LOD) |
> (intelObj->_MaxLevel - tObj->BaseLevel); /* mip count */
>
> + if (brw->gen >= 9)
> + surf[5] |= SET_FIELD(tr_mode, GEN9_SURFACE_TRMODE);
I would just write (and the same further down):
surf[5] |= SET_FIELD(surface_tiling_resource_mode(mt->tr_mode),
GEN9_SURFACE_TRMODE);
Or at least declare 'tr_mode' as constant.
Up to you, and in any case:
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
> +
> if (aux_mt) {
> surf[6] = SET_FIELD(mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
> SET_FIELD((aux_mt->pitch / 128) - 1, GEN8_SURFACE_AUX_PITCH)
> |
> @@ -318,6 +336,7 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
> unsigned height = mt->logical_height0;
> unsigned pitch = mt->pitch;
> uint32_t tiling = mt->tiling;
> + unsigned tr_mode = surface_tiling_resource_mode(mt->tr_mode);
> uint32_t format = 0;
> uint32_t surf_type;
> bool is_array = false;
> @@ -398,6 +417,9 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
>
> surf[5] = irb->mt_level - irb->mt->first_level;
>
> + if (brw->gen >= 9)
> + surf[5] |= SET_FIELD(tr_mode, GEN9_SURFACE_TRMODE);
> +
> if (aux_mt) {
> surf[6] = SET_FIELD(mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
> SET_FIELD((aux_mt->pitch / 128) - 1, GEN8_SURFACE_AUX_PITCH)
> |
> --
> 2.3.4
>
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