--- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp index 91a3f65..1ef4602 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp @@ -25,6 +25,7 @@ #include "glsl/ir_optimization.h" #include "glsl/nir/glsl_to_nir.h" #include "brw_fs.h" +#include "brw_nir.h" static void nir_optimize(nir_shader *nir) @@ -149,6 +150,14 @@ fs_visitor::emit_nir_code() nir_convert_from_ssa(nir); nir_validate_shader(nir); + /* This is the last pass we run before we start emitting stuff. It + * determines when we need to insert boolean resolves on GEN <= 5. We + * run it last because it stashes data in instr->pass_flags and we don't + * want that to be squashed by other NIR passes. + */ + if (brw->gen <= 5) + brw_nir_analize_boolean_resolves(nir); + /* emit the arrays used for inputs and outputs - load/store intrinsics will * be converted to reads/writes of these arrays */ @@ -1263,6 +1272,18 @@ fs_visitor::nir_emit_alu(nir_alu_instr *instr) default: unreachable("unhandled instruction"); } + + /* If we need to do a boolean resolve, replace the result with -(x & 1) + * to convert it from junk in the top 31 bits and the actual boolean in + * the bottom bit to the NIR standard of 0/~0. + */ + if (brw->gen <= 5 && + (instr->instr.pass_flags & BRW_NIR_BOOLEAN_MASK) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE) { + fs_reg masked = vgrf(glsl_type::int_type); + emit(AND(masked, result, fs_reg(1))); + masked.negate = true; + emit(MOV(result, masked)); + } } fs_reg -- 2.3.2 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev