From: Dave Airlie <airl...@redhat.com>
There was some code here to avoid MULADD on r600/r700, however some
recent changes caused some tests to start failing on evergreen as well.
(cayman has no T slot).
It seems likely there are some issues with writing a register in XYZW slots
and reading the same registers in T slot, but I can't say for sure,
docs aren't saying anything.
It seems easier to just not schedule op3 instructions in T slots for now.
This fixes
tests/spec/glsl-1.10/execution/variable-indexing/fs-temp-array-mat2-index-col-row-rd.shader_test
on rv630 and barts for me, since
it broke with the recent fixes from Glenn.
Signed-off-by: Dave Airlie <airl...@redhat.com>
---
src/gallium/drivers/r600/sb/sb_sched.cpp | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/r600/sb/sb_sched.cpp
b/src/gallium/drivers/r600/sb/sb_sched.cpp
index 4fbdc4f..320511a 100644
--- a/src/gallium/drivers/r600/sb/sb_sched.cpp
+++ b/src/gallium/drivers/r600/sb/sb_sched.cpp
@@ -1488,12 +1488,14 @@ unsigned post_scheduler::try_add_instruction(node *n) {
}
}
- // FIXME workaround for some problems with MULADD in trans slot
on r700,
- // (is it really needed on r600?)
- if ((a->bc.op == ALU_OP3_MULADD || a->bc.op ==
ALU_OP3_MULADD_IEEE) &&
- !ctx.is_egcm()) {
+ /*
+ * There seems to be some problem with OP3 instructions in
trans slots
+ * on r600->evergreen (cayman has no trans) - just avoid for now
+ * I suspect a problem with we write a register in X slot, but
are
+ * reading from same register in T slot but can't say for sure.
- airlied
+ */
+ if (a->bc.op_ptr->src_count == 3)
allowed_slots &= 0x0F;
- }
if (!allowed_slots) {
PSC_DUMP( sblog << " no suitable slots\n"; );
--
2.1.0
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