On Friday, February 06, 2015 07:23:27 PM Francisco Jerez wrote:
> ---
> src/mesa/drivers/dri/i965/brw_defines.h | 3 +++
> src/mesa/drivers/dri/i965/gen7_wm_state.c | 7 +++++++
> src/mesa/drivers/dri/i965/gen8_depth_state.c | 12 ++++++++----
> src/mesa/drivers/dri/i965/gen8_ps_state.c | 13 +++++++++++++
> 4 files changed, 31 insertions(+), 4 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
> b/src/mesa/drivers/dri/i965/brw_defines.h
> index 7b151f6..4a3acee 100644
> --- a/src/mesa/drivers/dri/i965/brw_defines.h
> +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> @@ -2220,6 +2220,9 @@ enum brw_wm_barycentric_interp_mode {
> # define GEN7_WM_KILL_ENABLE (1 << 25)
> # define GEN7_WM_COMPUTED_DEPTH_MODE_SHIFT 23
> # define GEN7_WM_USES_SOURCE_DEPTH (1 << 20)
> +# define GEN7_WM_EARLY_DS_CONTROL_NORMAL (0 << 21)
> +# define GEN7_WM_EARLY_DS_CONTROL_PSEXEC (1 << 21)
> +# define GEN7_WM_EARLY_DS_CONTROL_PREPS (2 << 21)
> # define GEN7_WM_USES_SOURCE_W (1 << 19)
> # define GEN7_WM_POSITION_ZW_PIXEL (0 << 17)
> # define GEN7_WM_POSITION_ZW_CENTROID (2 << 17)
> diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c
> b/src/mesa/drivers/dri/i965/gen7_wm_state.c
> index 31b1d48..744bba3 100644
> --- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
> +++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
> @@ -105,6 +105,13 @@ upload_wm_state(struct brw_context *brw)
> dw1 |= GEN7_WM_USES_INPUT_COVERAGE_MASK;
> }
>
> + if (shader) {
> + if (shader->EarlyFragmentTests)
> + dw1 |= GEN7_WM_EARLY_DS_CONTROL_PREPS;
> + else if (shader->NumImages)
> + dw1 |= GEN7_WM_EARLY_DS_CONTROL_PSEXEC;
> + }
> +
> BEGIN_BATCH(3);
> OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
> OUT_BATCH(dw1);
> diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c
> b/src/mesa/drivers/dri/i965/gen8_depth_state.c
> index e428089..7b4741a 100644
> --- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
> +++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
> @@ -241,10 +241,13 @@ pma_fix_enable(const struct brw_context *brw)
> */
> const bool hiz_enabled = depth_irb &&
> intel_renderbuffer_has_hiz(depth_irb);
>
> - /* 3DSTATE_WM::Early Depth/Stencil Control != EDSC_PREPS (2).
> - * We always leave this set to EDSC_NORMAL (0).
> + /* BRW_NEW_FRAGMENT_PROGRAM:
> + * 3DSTATE_WM::Early Depth/Stencil Control != EDSC_PREPS (2).
> */
> - const bool edsc_not_preps = true;
> + struct gl_shader_program *prog = ctx->Shader._CurrentFragmentProgram;
> + struct gl_shader *shader =
> + prog ? prog->_LinkedShaders[MESA_SHADER_FRAGMENT] : NULL;
> + const bool edsc_not_preps = !(shader && shader->EarlyFragmentTests);
>
> /* 3DSTATE_PS_EXTRA::PixelShaderValid is always true. */
> const bool pixel_shader_valid = true;
> @@ -369,7 +372,8 @@ const struct brw_tracked_state gen8_pma_fix = {
> _NEW_DEPTH |
> _NEW_MULTISAMPLE |
> _NEW_STENCIL,
> - .brw = BRW_NEW_FS_PROG_DATA,
> + .brw = BRW_NEW_FRAGMENT_PROGRAM |
> + BRW_NEW_FS_PROG_DATA,
> },
> .emit = gen8_emit_pma_stall_workaround
> };
> diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c
> b/src/mesa/drivers/dri/i965/gen8_ps_state.c
> index b932437..97c2d41 100644
> --- a/src/mesa/drivers/dri/i965/gen8_ps_state.c
> +++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c
> @@ -86,6 +86,10 @@ static void
> upload_wm_state(struct brw_context *brw)
> {
> struct gl_context *ctx = &brw->ctx;
> + /* BRW_NEW_FRAGMENT_PROGRAM */
> + struct gl_shader_program *prog = ctx->Shader._CurrentFragmentProgram;
> + struct gl_shader *shader =
> + prog ? prog->_LinkedShaders[MESA_SHADER_FRAGMENT] : NULL;
> uint32_t dw1 = 0;
>
> dw1 |= GEN7_WM_STATISTICS_ENABLE;
> @@ -105,6 +109,14 @@ upload_wm_state(struct brw_context *brw)
> dw1 |= brw->wm.prog_data->barycentric_interp_modes <<
> GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
>
> + /* BRW_NEW_FRAGMENT_PROGRAM */
> + if (shader) {
> + if (shader->EarlyFragmentTests)
> + dw1 |= GEN7_WM_EARLY_DS_CONTROL_PREPS;
> + else if (shader->NumImages)
> + dw1 |= GEN7_WM_EARLY_DS_CONTROL_PSEXEC;
> + }
> +
> BEGIN_BATCH(2);
> OUT_BATCH(_3DSTATE_WM << 16 | (2 - 2));
> OUT_BATCH(dw1);
> @@ -116,6 +128,7 @@ const struct brw_tracked_state gen8_wm_state = {
> .mesa = _NEW_LINE |
> _NEW_POLYGON,
> .brw = BRW_NEW_CONTEXT |
> + BRW_NEW_FRAGMENT_PROGRAM |
> BRW_NEW_FS_PROG_DATA,
> },
> .emit = upload_wm_state,Aha! So that's what those hardware bits are for. Nice. What do you think about just storing the EDSC mode in brw_wm_prog_data, and using it directly in the state upload code? You wouldn't have to get at the gl_shader from the PMA stall path, then. Either way, Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
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