On 12/02/2014 03:51 AM, Kenneth Graunke wrote: > Commit c0347705 changed the Gen6-7 code to use ctx->_Shader rather than > ctx->Shader, but neglected to change the Gen4-5 or Gen8+ code. > > This might fix SSO related bugs, but ALT mode is only used for ARB > programs, so if there's an actual problem, it's likely no one would > run into it.
I think the Gen8 code may not have existed upstream when I made the other changes. I'm not sure how the Gen4-5 parts got missed... This patch is Reviewed-by: Ian Romanick <ian.d.roman...@intel.com> > Signed-off-by: Kenneth Graunke <kenn...@whitecape.org> > --- > src/mesa/drivers/dri/i965/brw_vs_state.c | 2 +- > src/mesa/drivers/dri/i965/brw_wm_state.c | 2 +- > src/mesa/drivers/dri/i965/gen8_ps_state.c | 2 +- > src/mesa/drivers/dri/i965/gen8_vs_state.c | 2 +- > 4 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/src/mesa/drivers/dri/i965/brw_vs_state.c > b/src/mesa/drivers/dri/i965/brw_vs_state.c > index 998a225..abd6771 100644 > --- a/src/mesa/drivers/dri/i965/brw_vs_state.c > +++ b/src/mesa/drivers/dri/i965/brw_vs_state.c > @@ -60,7 +60,7 @@ brw_upload_vs_unit(struct brw_context *brw) > /* Use ALT floating point mode for ARB vertex programs, because they > * require 0^0 == 1. > */ > - if (brw->ctx.Shader.CurrentProgram[MESA_SHADER_VERTEX] == NULL) > + if (brw->ctx._Shader->CurrentProgram[MESA_SHADER_VERTEX] == NULL) > vs->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754; > else > vs->thread1.floating_point_mode = BRW_FLOATING_POINT_IEEE_754; > diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c > b/src/mesa/drivers/dri/i965/brw_wm_state.c > index 12cbc72..d2903c7 100644 > --- a/src/mesa/drivers/dri/i965/brw_wm_state.c > +++ b/src/mesa/drivers/dri/i965/brw_wm_state.c > @@ -119,7 +119,7 @@ brw_upload_wm_unit(struct brw_context *brw) > * rendering, CurrentProgram[MESA_SHADER_FRAGMENT] is used for this check > * to differentiate between the GLSL and non-GLSL cases. > */ > - if (ctx->Shader.CurrentProgram[MESA_SHADER_FRAGMENT] == NULL) > + if (ctx->_Shader->CurrentProgram[MESA_SHADER_FRAGMENT] == NULL) > wm->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754; > else > wm->thread1.floating_point_mode = BRW_FLOATING_POINT_IEEE_754; > diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c > b/src/mesa/drivers/dri/i965/gen8_ps_state.c > index 3aa0ef3..a3ce1d4 100644 > --- a/src/mesa/drivers/dri/i965/gen8_ps_state.c > +++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c > @@ -146,7 +146,7 @@ upload_ps_state(struct brw_context *brw) > * rendering, CurrentFragmentProgram is used for this check to > * differentiate between the GLSL and non-GLSL cases. > */ > - if (ctx->Shader.CurrentProgram[MESA_SHADER_FRAGMENT] == NULL) > + if (ctx->_Shader->CurrentProgram[MESA_SHADER_FRAGMENT] == NULL) > dw3 |= GEN7_PS_FLOATING_POINT_MODE_ALT; > > /* 3DSTATE_PS expects the number of threads per PSD, which is always 64; > diff --git a/src/mesa/drivers/dri/i965/gen8_vs_state.c > b/src/mesa/drivers/dri/i965/gen8_vs_state.c > index 00f2731..5a2021f 100644 > --- a/src/mesa/drivers/dri/i965/gen8_vs_state.c > +++ b/src/mesa/drivers/dri/i965/gen8_vs_state.c > @@ -42,7 +42,7 @@ upload_vs_state(struct brw_context *brw) > /* Use ALT floating point mode for ARB vertex programs, because they > * require 0^0 == 1. > */ > - if (ctx->Shader.CurrentProgram[MESA_SHADER_VERTEX] == NULL) > + if (ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX] == NULL) > floating_point_mode = GEN6_VS_FLOATING_POINT_MODE_ALT; > > BEGIN_BATCH(9); > _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
