This flag signals that we have a SIMD8 VS shader so we can set up the
corresponding state accordingly. This boils down to setting
the BDW+ SIMD8 enable bit in 3DSTATE_VS and making UBO and pull
constant buffers use dword pitch.
Signed-off-by: Kristian Høgsberg <k...@bitplanet.net>
---
src/mesa/drivers/dri/i965/brw_context.h | 5 ++++-
src/mesa/drivers/dri/i965/brw_defines.h | 2 ++
src/mesa/drivers/dri/i965/brw_gs_surface_state.c | 2 +-
src/mesa/drivers/dri/i965/brw_vs_surface_state.c | 10 ++++++++--
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 7 ++++---
src/mesa/drivers/dri/i965/gen8_vs_state.c | 2 ++
6 files changed, 21 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index eb37e75..e7cd30f 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -543,6 +543,8 @@ struct brw_vec4_prog_data {
* is the size of the URB entry used for output.
*/
GLuint urb_entry_size;
+
+ bool simd8;
};
@@ -1599,7 +1601,8 @@ brw_update_sol_surface(struct brw_context *brw,
void brw_upload_ubo_surfaces(struct brw_context *brw,
struct gl_shader *shader,
struct brw_stage_state *stage_state,
- struct brw_stage_prog_data *prog_data);
+ struct brw_stage_prog_data *prog_data,
+ bool dword_pitch);
void brw_upload_abo_surfaces(struct brw_context *brw,
struct gl_shader_program *prog,
struct brw_stage_state *stage_state,
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 650fdb9..900d8cf 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1688,6 +1688,8 @@ enum brw_message_target {
# define GEN6_VS_STATISTICS_ENABLE (1 << 10)
# define GEN6_VS_CACHE_DISABLE (1 << 1)
# define GEN6_VS_ENABLE (1 << 0)
+/* Gen8+ DW7 */
+# define GEN8_VS_SIMD8_ENABLE (1 << 2)
/* Gen8+ DW8 */
# define GEN8_VS_URB_ENTRY_OUTPUT_OFFSET_SHIFT 21
# define GEN8_VS_URB_OUTPUT_LENGTH_SHIFT 16
diff --git a/src/mesa/drivers/dri/i965/brw_gs_surface_state.c
b/src/mesa/drivers/dri/i965/brw_gs_surface_state.c
index 2c2ba56..42cdddb 100644
--- a/src/mesa/drivers/dri/i965/brw_gs_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_gs_surface_state.c
@@ -77,7 +77,7 @@ brw_upload_gs_ubo_surfaces(struct brw_context *brw)
/* CACHE_NEW_GS_PROG */
brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_GEOMETRY],
- &brw->gs.base, &brw->gs.prog_data->base.base);
+ &brw->gs.base, &brw->gs.prog_data->base.base, false);
}
const struct brw_tracked_state brw_gs_ubo_surfaces = {
diff --git a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
index 1cc96cf..24bc06d 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
@@ -112,6 +112,7 @@ static void
brw_upload_vs_pull_constants(struct brw_context *brw)
{
struct brw_stage_state *stage_state = &brw->vs.base;
+ bool dword_pitch;
/* BRW_NEW_VERTEX_PROGRAM */
struct brw_vertex_program *vp =
@@ -120,9 +121,11 @@ brw_upload_vs_pull_constants(struct brw_context *brw)
/* CACHE_NEW_VS_PROG */
const struct brw_stage_prog_data *prog_data = &brw->vs.prog_data->base.base;
+ dword_pitch = brw->vs.prog_data->base.simd8;
+
/* _NEW_PROGRAM_CONSTANTS */
brw_upload_pull_constants(brw, BRW_NEW_VS_CONSTBUF, &vp->program.Base,
- stage_state, prog_data, false);
+ stage_state, prog_data, dword_pitch);
}
const struct brw_tracked_state brw_vs_pull_constants = {
@@ -141,13 +144,16 @@ brw_upload_vs_ubo_surfaces(struct brw_context *brw)
/* _NEW_PROGRAM */
struct gl_shader_program *prog =
ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX];
+ bool dword_pitch;
if (!prog)
return;
/* CACHE_NEW_VS_PROG */
+ dword_pitch = brw->vs.prog_data->base.simd8;
brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_VERTEX],
- &brw->vs.base, &brw->vs.prog_data->base.base);
+ &brw->vs.base, &brw->vs.prog_data->base.base,
+ dword_pitch);
}
const struct brw_tracked_state brw_vs_ubo_surfaces = {
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index ef46dd7..ec86841 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -837,7 +837,8 @@ void
brw_upload_ubo_surfaces(struct brw_context *brw,
struct gl_shader *shader,
struct brw_stage_state *stage_state,
- struct brw_stage_prog_data *prog_data)
+ struct brw_stage_prog_data *prog_data,
+ bool dword_pitch)
{
struct gl_context *ctx = &brw->ctx;
@@ -865,7 +866,7 @@ brw_upload_ubo_surfaces(struct brw_context *brw,
brw_create_constant_surface(brw, bo, binding->Offset,
bo->size - binding->Offset,
&surf_offsets[i],
- shader->Stage == MESA_SHADER_FRAGMENT);
+ dword_pitch);
}
if (shader->NumUniformBlocks)
@@ -884,7 +885,7 @@ brw_upload_wm_ubo_surfaces(struct brw_context *brw)
/* CACHE_NEW_WM_PROG */
brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_FRAGMENT],
- &brw->wm.base, &brw->wm.prog_data->base);
+ &brw->wm.base, &brw->wm.prog_data->base, true);
}
const struct brw_tracked_state brw_wm_ubo_surfaces = {
diff --git a/src/mesa/drivers/dri/i965/gen8_vs_state.c
b/src/mesa/drivers/dri/i965/gen8_vs_state.c
index 0cc4f0c..14e2995 100644
--- a/src/mesa/drivers/dri/i965/gen8_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_vs_state.c
@@ -69,8 +69,10 @@ upload_vs_state(struct brw_context *brw)
(prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
(0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
+ uint32_t simd8_enable = prog_data->simd8 ? GEN8_VS_SIMD8_ENABLE : 0;
OUT_BATCH(((brw->max_vs_threads - 1) << HSW_VS_MAX_THREADS_SHIFT) |
GEN6_VS_STATISTICS_ENABLE |
+ simd8_enable |
GEN6_VS_ENABLE);
/* _NEW_TRANSFORM */
--
2.1.0
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