On Wednesday, November 12, 2014 10:53:29 AM Chris Wilson wrote:
> On Wed, Nov 12, 2014 at 11:39:28AM +0100, Daniel Vetter wrote:
> > On Wed, Nov 12, 2014 at 01:33:01AM -0800, Kenneth Graunke wrote:
> > > +/* Implement the WaCsStallAtEveryFourthPipecontrol workaround on IVB,
BYT:
> > > + *
> > > + * "Every 4th PIPE_CONTROL command, not counting the PIPE_CONTROL with
> > > + * only read-cache-invalidate bit(s) set, must have a CS_STALL bit
set."
> > > + *
> > > + * Note that the kernel does CS stalls between batches, so we only need
> > > + * to count them within a batch.
> > > + */
> > > +static uint32_t
> > > +gen7_cs_stall_every_four_pipe_controls(struct brw_context *brw,
uint32_t flags)
> > > +{
> > > + if (brw->gen == 7 && brw->is_haswell) {
>
> The comment says for IVB,BYT, the code here only applies to HSW.
> -ChrisD'oh...meant to put a ! there. Thanks Chris! I retested on IVB (now that it actually does something), and it still has no Piglit regressions. Daniel, I also like your suggestion about ++. Changed for v2 :)
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