On Tue, Oct 14, 2014 at 3:03 PM, Jason Ekstrand <ja...@jlekstrand.net>
wrote:
>
>
> On Mon, Oct 13, 2014 at 9:54 PM, Kenneth Graunke <kenn...@whitecape.org>
> wrote:
>
>> From: Connor Abbott <connor.abb...@intel.com>
>>
>> At this point, the only thing it's used for is the opcode.
>>
>> Signed-off-by: Connor Abbott <connor.abb...@intel.com>
>> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
>> ---
>> src/mesa/drivers/dri/i965/brw_fs.h | 6 ++---
>> src/mesa/drivers/dri/i965/brw_fs_fp.cpp | 6 ++---
>> src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 35
>> ++++++++++++++--------------
>> 3 files changed, 23 insertions(+), 24 deletions(-)
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
>> b/src/mesa/drivers/dri/i965/brw_fs.h
>> index 5441031..2615e40 100644
>> --- a/src/mesa/drivers/dri/i965/brw_fs.h
>> +++ b/src/mesa/drivers/dri/i965/brw_fs.h
>> @@ -470,18 +470,18 @@ public:
>> void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
>> fs_reg rescale_texcoord(fs_reg coordinate, const glsl_type
>> *coord_type,
>> bool is_rect, uint32_t sampler, int texunit);
>> - fs_inst *emit_texture_gen4(ir_texture *ir, fs_reg dst,
>> + fs_inst *emit_texture_gen4(ir_texture_opcode op, fs_reg dst,
>> fs_reg coordinate, int coord_components,
>> fs_reg shadow_comp,
>> fs_reg lod, fs_reg lod2, int
>> grad_components,
>> uint32_t sampler);
>> - fs_inst *emit_texture_gen5(ir_texture *ir, fs_reg dst,
>> + fs_inst *emit_texture_gen5(ir_texture_opcode op, fs_reg dst,
>> fs_reg coordinate, int coord_components,
>> fs_reg shadow_comp,
>> fs_reg lod, fs_reg lod2, int
>> grad_components,
>> fs_reg sample_index, uint32_t sampler,
>> bool has_offset);
>> - fs_inst *emit_texture_gen7(ir_texture *ir, fs_reg dst,
>> + fs_inst *emit_texture_gen7(ir_texture_opcode op, fs_reg dst,
>> fs_reg coordinate, int coord_components,
>> fs_reg shadow_comp,
>> fs_reg lod, fs_reg lod2, int
>> grad_components,
>> diff --git a/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
>> b/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
>> index a77769b..99cdecb 100644
>> --- a/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
>> +++ b/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
>> @@ -487,11 +487,11 @@ fs_visitor::emit_fragment_program_code()
>>
>> fs_inst *inst;
>> if (brw->gen >= 7) {
>> - inst = emit_texture_gen7(ir, dst, coordinate,
>> coord_components, shadow_c, lod, dpdy, 0, sample_index, fs_reg(0u),
>> fs_reg(fpi->TexSrcUnit), texel_offset);
>> + inst = emit_texture_gen7(ir->op, dst, coordinate,
>> coord_components, shadow_c, lod, dpdy, 0, sample_index, fs_reg(0u),
>> fs_reg(fpi->TexSrcUnit), texel_offset);
>> } else if (brw->gen >= 5) {
>> - inst = emit_texture_gen5(ir, dst, coordinate,
>> coord_components, shadow_c, lod, dpdy, 0, sample_index, fpi->TexSrcUnit,
>> false);
>> + inst = emit_texture_gen5(ir->op, dst, coordinate,
>> coord_components, shadow_c, lod, dpdy, 0, sample_index, fpi->TexSrcUnit,
>> false);
>> } else {
>> - inst = emit_texture_gen4(ir, dst, coordinate,
>> coord_components, shadow_c, lod, dpdy, 0, fpi->TexSrcUnit);
>> + inst = emit_texture_gen4(ir->op, dst, coordinate,
>> coord_components, shadow_c, lod, dpdy, 0, fpi->TexSrcUnit);
>> }
>>
>> inst->shadow_compare = fpi->TexShadow;
>> diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
>> b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
>> index c741ca3..2251bae 100644
>> --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
>> +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
>> @@ -1166,7 +1166,7 @@ fs_visitor::visit(ir_assignment *ir)
>> }
>>
>> fs_inst *
>> -fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst,
>> +fs_visitor::emit_texture_gen4(ir_texture_opcode op, fs_reg dst,
>> fs_reg coordinate, int coord_components,
>> fs_reg shadow_c,
>> fs_reg lod, fs_reg dPdy, int
>> grad_components,
>> @@ -1194,13 +1194,13 @@ fs_visitor::emit_texture_gen4(ir_texture *ir,
>> fs_reg dst,
>> }
>> mlen += 3;
>>
>> - if (ir->op == ir_tex) {
>> + if (op == ir_tex) {
>> /* There's no plain shadow compare message, so we use shadow
>> * compare with a bias of 0.0.
>> */
>> emit(MOV(fs_reg(MRF, base_mrf + mlen), fs_reg(0.0f)));
>> mlen++;
>> - } else if (ir->op == ir_txb || ir->op == ir_txl) {
>> + } else if (op == ir_txb || op == ir_txl) {
>> emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
>> mlen++;
>> } else {
>> @@ -1209,7 +1209,7 @@ fs_visitor::emit_texture_gen4(ir_texture *ir,
>> fs_reg dst,
>>
>> emit(MOV(fs_reg(MRF, base_mrf + mlen), shadow_c));
>> mlen++;
>> - } else if (ir->op == ir_tex) {
>> + } else if (op == ir_tex) {
>> for (int i = 0; i < coord_components; i++) {
>> emit(MOV(fs_reg(MRF, base_mrf + mlen + i), coordinate));
>> coordinate = offset(coordinate, 1);
>> @@ -1220,7 +1220,7 @@ fs_visitor::emit_texture_gen4(ir_texture *ir,
>> fs_reg dst,
>> }
>> /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
>> mlen += 3;
>> - } else if (ir->op == ir_txd) {
>> + } else if (op == ir_txd) {
>> fs_reg &dPdx = lod;
>>
>> for (int i = 0; i < coord_components; i++) {
>> @@ -1255,7 +1255,7 @@ fs_visitor::emit_texture_gen4(ir_texture *ir,
>> fs_reg dst,
>> dPdy = offset(dPdy, 1);
>> }
>> mlen += MAX2(grad_components, 2);
>> - } else if (ir->op == ir_txs) {
>> + } else if (op == ir_txs) {
>> /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead.
>> */
>> simd16 = true;
>> emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), lod));
>> @@ -1265,7 +1265,7 @@ fs_visitor::emit_texture_gen4(ir_texture *ir,
>> fs_reg dst,
>> * instructions. We'll need to do SIMD16 here.
>> */
>> simd16 = true;
>> - assert(ir->op == ir_txb || ir->op == ir_txl || ir->op == ir_txf);
>> + assert(op == ir_txb || op == ir_txl || op == ir_txf);
>>
>> for (int i = 0; i < coord_components; i++) {
>> emit(MOV(fs_reg(MRF, base_mrf + mlen + i * 2, coordinate.type),
>> @@ -1300,8 +1300,7 @@ fs_visitor::emit_texture_gen4(ir_texture *ir,
>> fs_reg dst,
>> }
>>
>
> Uh... This doesn't build. You're missing a hunk inside the "if (simd16)"
> block to use the type from dst rather than brw_type_for_base_type(ir->type).
>
In particular, squash in this:
http://cgit.freedesktop.org/~jekstrand/mesa/commit/?h=nir-texture-rebase&id=c885f41e702adcb504a737ed6bf916ae2e5e51d0
>
>
>>
>> enum opcode opcode;
>> -
>> - switch (ir->op) {
>> + switch (op) {
>> case ir_tex: opcode = SHADER_OPCODE_TEX; break;
>> case ir_txb: opcode = FS_OPCODE_TXB; break;
>> case ir_txl: opcode = SHADER_OPCODE_TXL; break;
>> @@ -1338,7 +1337,7 @@ fs_visitor::emit_texture_gen4(ir_texture *ir,
>> fs_reg dst,
>> * surprising in the disassembly.
>> */
>> fs_inst *
>> -fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst,
>> +fs_visitor::emit_texture_gen5(ir_texture_opcode op, fs_reg dst,
>> fs_reg coordinate, int vector_elements,
>> fs_reg shadow_c,
>> fs_reg lod, fs_reg lod2, int
>> grad_components,
>> @@ -1374,7 +1373,7 @@ fs_visitor::emit_texture_gen5(ir_texture *ir,
>> fs_reg dst,
>> }
>>
>> enum opcode opcode;
>> - switch (ir->op) {
>> + switch (op) {
>> case ir_tex:
>> opcode = SHADER_OPCODE_TEX;
>> break;
>> @@ -1479,7 +1478,7 @@ is_high_sampler(struct brw_context *brw, fs_reg
>> sampler)
>> }
>>
>> fs_inst *
>> -fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst,
>> +fs_visitor::emit_texture_gen7(ir_texture_opcode op, fs_reg dst,
>> fs_reg coordinate, int coord_components,
>> fs_reg shadow_c,
>> fs_reg lod, fs_reg lod2, int
>> grad_components,
>> @@ -1495,7 +1494,7 @@ fs_visitor::emit_texture_gen7(ir_texture *ir,
>> fs_reg dst,
>> }
>> int length = 0;
>>
>> - if (ir->op == ir_tg4 || offset_value.file != BAD_FILE ||
>> + if (op == ir_tg4 || offset_value.file != BAD_FILE ||
>> is_high_sampler(brw, sampler)) {
>> /* For general texture offsets (no txf workaround), we need a
>> header to
>> * put them in. Note that for SIMD16 we're making space for two
>> actual
>> @@ -1522,7 +1521,7 @@ fs_visitor::emit_texture_gen7(ir_texture *ir,
>> fs_reg dst,
>> bool coordinate_done = false;
>>
>> /* Set up the LOD info */
>> - switch (ir->op) {
>> + switch (op) {
>> case ir_tex:
>> case ir_lod:
>> break;
>> @@ -1656,7 +1655,7 @@ fs_visitor::emit_texture_gen7(ir_texture *ir,
>> fs_reg dst,
>>
>> /* Generate the SEND */
>> enum opcode opcode;
>> - switch (ir->op) {
>> + switch (op) {
>> case ir_tex: opcode = SHADER_OPCODE_TEX; break;
>> case ir_txb: opcode = FS_OPCODE_TXB; break;
>> case ir_txl: opcode = SHADER_OPCODE_TXL; break;
>> @@ -2003,19 +2002,19 @@ fs_visitor::visit(ir_texture *ir)
>> fs_reg dst = fs_reg(this,
>> glsl_type::get_instance(ir->type->base_type, 4, 1));
>>
>> if (brw->gen >= 7) {
>> - inst = emit_texture_gen7(ir, dst, coordinate, coord_components,
>> + inst = emit_texture_gen7(ir->op, dst, coordinate, coord_components,
>> shadow_comparitor,
>> lod, lod2, grad_components,
>> sample_index, mcs, sampler_reg,
>> offset_value);
>> } else if (brw->gen >= 5) {
>> - inst = emit_texture_gen5(ir, dst, coordinate, coord_components,
>> + inst = emit_texture_gen5(ir->op, dst, coordinate, coord_components,
>> shadow_comparitor,
>> lod, lod2, grad_components,
>> sample_index, sampler,
>> ir->offset != NULL);
>> } else {
>> - inst = emit_texture_gen4(ir, dst, coordinate, coord_components,
>> + inst = emit_texture_gen4(ir->op, dst, coordinate, coord_components,
>> shadow_comparitor,
>> lod, lod2, grad_components,
>> sampler);
>> --
>> 2.1.2
>>
>> _______________________________________________
>> mesa-dev mailing list
>> mesa-dev@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/mesa-dev
>>
>
>
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