UBO loads can be boolean-valued expressions, too, so we need to handle them in emit_bool_to_cond_code() and emit_if_gen6().
However, unlike most expressions, it doesn't make sense to evaluate their operands, then do something with the results. We just want to evaluate the UBO load as a whole---which performs the read from memory---then load the boolean result into the flag register. Instead of adding code to handle it, we can simply bypass the ir_expression handling, and fall through to the default code, which will do exactly that. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83468 Signed-off-by: Kenneth Graunke <kenn...@whitecape.org> Cc: Ian Romanick <i...@freedesktop.org> Cc: mesa-sta...@lists.freedesktop.org --- src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 4 ++-- src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index d7e3120..ff1e716 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -2235,7 +2235,7 @@ fs_visitor::emit_bool_to_cond_code(ir_rvalue *ir) { ir_expression *expr = ir->as_expression(); - if (!expr) { + if (!expr || expr->operation == ir_binop_ubo_load) { ir->accept(this); fs_inst *inst = emit(AND(reg_null_d, this->result, fs_reg(1))); @@ -2363,7 +2363,7 @@ fs_visitor::emit_if_gen6(ir_if *ir) { ir_expression *expr = ir->condition->as_expression(); - if (expr) { + if (expr && expr->operation != ir_binop_ubo_load) { fs_reg op[3]; fs_inst *inst; fs_reg temp; diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp index 93ea63d..1e823da 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp @@ -776,7 +776,7 @@ vec4_visitor::emit_bool_to_cond_code(ir_rvalue *ir, *predicate = BRW_PREDICATE_NORMAL; - if (expr) { + if (expr && expr->operation != ir_binop_ubo_load) { src_reg op[3]; vec4_instruction *inst; @@ -897,7 +897,7 @@ vec4_visitor::emit_if_gen6(ir_if *ir) { ir_expression *expr = ir->condition->as_expression(); - if (expr) { + if (expr && expr->operation != ir_binop_ubo_load) { src_reg op[3]; dst_reg temp; -- 2.1.0 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
