From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeonsi/si_blit.c | 15 +++++++++++++++
src/gallium/drivers/radeonsi/si_pipe.h | 1 +
src/gallium/drivers/radeonsi/si_state.c | 4 ++--
src/gallium/drivers/radeonsi/si_state_draw.c | 3 +++
4 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_blit.c
b/src/gallium/drivers/radeonsi/si_blit.c
index 87c8fa9..4e77d74 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -328,6 +328,9 @@ static void si_clear(struct pipe_context *ctx, unsigned
buffers,
{
struct si_context *sctx = (struct si_context *)ctx;
struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
+ struct pipe_surface *zsbuf = fb->zsbuf;
+ struct r600_texture *zstex =
+ zsbuf ? (struct r600_texture*)zsbuf->texture : NULL;
if (buffers & PIPE_CLEAR_COLOR) {
evergreen_do_fast_color_clear(&sctx->b, fb,
&sctx->framebuffer.atom,
@@ -354,11 +357,23 @@ static void si_clear(struct pipe_context *ctx, unsigned
buffers,
}
}
+ if (buffers & PIPE_CLEAR_DEPTH &&
+ zstex && zstex->htile_buffer &&
+ zsbuf->u.tex.level == 0 &&
+ zsbuf->u.tex.first_layer == 0 &&
+ zsbuf->u.tex.last_layer == util_max_layer(&zstex->resource.b.b, 0))
{
+ zstex->depth_clear_value = depth;
+ sctx->framebuffer.atom.dirty = true; /* updates DB_DEPTH_CLEAR
*/
+ sctx->db_depth_clear = true;
+ }
+
si_blitter_begin(ctx, SI_CLEAR);
util_blitter_clear(sctx->blitter, fb->width, fb->height,
util_framebuffer_get_num_layers(fb),
buffers, color, depth, stencil);
si_blitter_end(ctx);
+
+ sctx->db_depth_clear = false;
}
static void si_clear_render_target(struct pipe_context *ctx,
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h
b/src/gallium/drivers/radeonsi/si_pipe.h
index c4f3800..0a79983 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -164,6 +164,7 @@ struct si_context {
bool dbcb_stencil_copy_enabled;
unsigned dbcb_copy_sample;
bool db_inplace_flush_enabled;
+ bool db_depth_clear;
};
/* si_blit.c */
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index 9f7c065..3b429cf 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1926,7 +1926,7 @@ static void si_set_framebuffer_state(struct pipe_context
*ctx,
si_update_fb_blend_state(sctx);
sctx->framebuffer.atom.num_dw = state->nr_cbufs*15 + (8 -
state->nr_cbufs)*3;
- sctx->framebuffer.atom.num_dw += state->zsbuf ? 23 : 4;
+ sctx->framebuffer.atom.num_dw += state->zsbuf ? 26 : 4;
sctx->framebuffer.atom.num_dw += 3; /* WINDOW_SCISSOR_BR */
sctx->framebuffer.atom.num_dw += 18; /* MSAA sample locations */
sctx->framebuffer.atom.dirty = true;
@@ -2044,6 +2044,7 @@ static void si_emit_framebuffer_state(struct si_context
*sctx, struct r600_atom
radeon_emit(cs, zb->db_depth_slice); /*
R_02805C_DB_DEPTH_SLICE */
r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE,
zb->db_htile_surface);
+ r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR,
fui(rtex->depth_clear_value));
r600_write_context_reg(cs,
R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
zb->pa_su_poly_offset_db_fmt_cntl);
} else {
@@ -3088,7 +3089,6 @@ void si_init_config(struct si_context *sctx)
si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
- si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000);
si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index ea04138..a66337a 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -751,6 +751,9 @@ static void si_state_draw(struct si_context *sctx,
si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL,
S_028000_DEPTH_COMPRESS_DISABLE(1) |
S_028000_STENCIL_COMPRESS_DISABLE(1));
+ } else if (sctx->db_depth_clear) {
+ si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL,
+ S_028000_DEPTH_CLEAR_ENABLE(1));
} else {
si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, 0);
}
--
1.9.1
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