With a few tiny changes, we can just reuse the normal FB write handling.
I originally mistook the FS_OPCODE_BLORP_FB_WRITE opcode for the SIMD16
replicated data message used in certain BLORP color clears, when it was
actually just a normal SIMD16 message without a little bit of setup.
Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 8 ++------
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp | 3 ++-
src/mesa/drivers/dri/i965/brw_defines.h | 1 -
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 21 +--------------------
src/mesa/drivers/dri/i965/brw_shader.cpp | 2 --
5 files changed, 5 insertions(+), 30 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 92c92aa..3e384ed 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1734,11 +1734,7 @@ brw_blorp_blit_program::render_target_write()
/* If we may have killed pixels, then we need to send R0 and R1 in a header
* so that the render target knows which pixels we killed.
*/
- bool use_header = key->use_kill;
- if (use_header) {
- /* Copy R0/1 to MRF */
- emit_mov(retype(mrf_rt_write, BRW_REGISTER_TYPE_UD),
- retype(R0, BRW_REGISTER_TYPE_UD));
+ if (key->use_kill) {
mrf_offset += 2;
}
@@ -1755,7 +1751,7 @@ brw_blorp_blit_program::render_target_write()
mrf_rt_write,
base_mrf,
mrf_offset /* msg_length. TODO: Should be smaller for non-RGBA formats.
*/,
- use_header);
+ key->use_kill);
}
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
index 5a485df..c20a163 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
@@ -94,13 +94,14 @@ brw_blorp_eu_emitter::emit_render_target_write(const struct
brw_reg &src0,
unsigned msg_length,
bool use_header)
{
- fs_inst *inst = new (mem_ctx) fs_inst(FS_OPCODE_BLORP_FB_WRITE);
+ fs_inst *inst = new (mem_ctx) fs_inst(FS_OPCODE_FB_WRITE);
inst->src[0] = src0;
inst->base_mrf = msg_reg_nr;
inst->mlen = msg_length;
inst->header_present = use_header;
inst->target = BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX;
+ inst->eot = true;
insts.push_tail(inst);
}
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 3564041..658d94d 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -842,7 +842,6 @@ enum opcode {
* instructions.
*/
FS_OPCODE_FB_WRITE = 128,
- FS_OPCODE_BLORP_FB_WRITE,
SHADER_OPCODE_RCP,
SHADER_OPCODE_RSQ,
SHADER_OPCODE_SQRT,
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index d3509a0..19f7ef8 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -186,7 +186,7 @@ fs_generator::generate_fb_write(fs_inst *inst)
brw_imm_ud(0x1 << 11));
}
- if (inst->target > 0) {
+ if (fp && inst->target > 0) {
/* Set the render target index for choosing BLEND_STATE. */
brw_MOV(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE,
inst->base_mrf, 2),
@@ -231,21 +231,6 @@ fs_generator::generate_fb_write(fs_inst *inst)
}
}
-void
-fs_generator::generate_blorp_fb_write(fs_inst *inst)
-{
- brw_fb_WRITE(p,
- 16 /* dispatch_width */,
- inst->base_mrf,
- brw_reg_from_fs_reg(&inst->src[0]),
- BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
- inst->target,
- inst->mlen,
- 0,
- true,
- inst->header_present);
-}
-
/* Computes the integer pixel x,y values from the origin.
*
* This is the basis of gl_FragCoord computation, but is also used
@@ -1698,10 +1683,6 @@ fs_generator::generate_code(exec_list *instructions)
generate_fb_write(inst);
break;
- case FS_OPCODE_BLORP_FB_WRITE:
- generate_blorp_fb_write(inst);
- break;
-
case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
generate_mov_dispatch_to_flags(inst);
break;
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index 0033135..e22d1f2 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -402,8 +402,6 @@ brw_instruction_name(enum opcode op)
switch (op) {
case FS_OPCODE_FB_WRITE:
return "fb_write";
- case FS_OPCODE_BLORP_FB_WRITE:
- return "blorp_fb_write";
case SHADER_OPCODE_RCP:
return "rcp";
--
2.0.2
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