v3 has some changes suggested by Topi and Ken on the July 18 version. These patches do not have Reviewed-by: * 04 i965/gen6: Adjust render height in errata case for MSAA * 06 i965/gen6_depth_state.c: Remove (gen < 6) code paths * 10 i965/gen6 depth surface: calculate minimum array element being rendered * 11 i965/gen6 blorp depth: calculate base surface width/height * 13 i965/gen6 depth surface: program 3DSTATE_DEPTH_BUFFER to top of surface
Topi: I retained your r-b on 14-19, but they did change since I converted to using an enum like we discussed on the old patch 12/17. Ken: I think you essentially gave an r-b for the new 02/19. Let me know if I'm mistaken. Ken/Topi: Is the new commit message in patch 16/19 helpful? The goal for this series is to allow layered rendering to work with gen6. On gen6, it also fixes 10 failing piglit tests, 54 crashing piglit tests, and a performance regression bug (https://bugs.freedesktop.org/show_bug.cgi?id=56127). This series is available on this branch: git://people.freedesktop.org/~jljusten/mesa gen6-layered-v3 Jordan Justen (19): i965: Split gen6 renderbuffer surface state from gen5 and older i965/gen6_surface_state.c: Remove (gen < 6) code path i965/gen6: add support for layered renderbuffers i965/gen6: Adjust render height in errata case for MSAA i965: Split gen6 depth hiz state out from brw i965/gen6_depth_state.c: Remove (gen < 6) code paths i965/gen6 depth surface: calculate more specific surface type i965/gen6 depth surface: calculate depth (array size) for depth surface i965/gen6 depth surface: calculate LOD being rendered to i965/gen6 depth surface: calculate minimum array element being rendered i965/gen6 blorp depth: calculate base surface width/height i965/gen6 fbo: make unmatched depth/stencil configs return unsupported i965/gen6 depth surface: program 3DSTATE_DEPTH_BUFFER to top of surface i965: Change mipmap array_spacing_lod0 to array_layout (enum) i965: Allow forcing miptree->array_layout = ALL_SLICES_AT_EACH_LOD i965: Support array_layout == ALL_SLICES_AT_EACH_LOD for multiple LODs i965/gen6: Force tile alignment for each stencil/hiz LOD i965/gen6: Stencil/hiz needs an offset for LOD > 0 i965/gen6: Force ALL_SLICES_AT_EACH_LOD for separate stencil/hiz src/mesa/drivers/dri/i965/Makefile.sources | 2 + src/mesa/drivers/dri/i965/brw_blorp.cpp | 2 +- src/mesa/drivers/dri/i965/brw_blorp.h | 10 +- src/mesa/drivers/dri/i965/brw_context.c | 4 + src/mesa/drivers/dri/i965/brw_context.h | 10 + src/mesa/drivers/dri/i965/brw_defines.h | 4 + src/mesa/drivers/dri/i965/brw_misc_state.c | 4 +- src/mesa/drivers/dri/i965/brw_state.h | 3 + src/mesa/drivers/dri/i965/brw_tex_layout.c | 62 +++++- src/mesa/drivers/dri/i965/gen6_blorp.cpp | 115 ++++++---- src/mesa/drivers/dri/i965/gen6_depth_state.c | 260 ++++++++++++++++++++++ src/mesa/drivers/dri/i965/gen6_surface_state.c | 142 ++++++++++++ src/mesa/drivers/dri/i965/gen7_blorp.cpp | 2 +- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 6 +- src/mesa/drivers/dri/i965/intel_fbo.c | 9 +- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 42 ++-- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 33 ++- src/mesa/drivers/dri/i965/intel_tex.c | 3 +- src/mesa/drivers/dri/i965/intel_tex_image.c | 3 +- src/mesa/drivers/dri/i965/intel_tex_subimage.c | 3 +- src/mesa/drivers/dri/i965/intel_tex_validate.c | 3 +- 21 files changed, 628 insertions(+), 94 deletions(-) create mode 100644 src/mesa/drivers/dri/i965/gen6_depth_state.c create mode 100644 src/mesa/drivers/dri/i965/gen6_surface_state.c -- 2.0.1 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
