This patch series contains some improvements to the register allocator used by the i965 fs and vec4 backends and r300g. The most important patch is the last one, which causes many fragment shaders to gain SIMD16 as we make smarter decisions in the allocator. Full shader-db results are reproduced in the commit messages, but here's the summary for the whole series:
total instructions in shared programs: 4545447 -> 4545411 (-0.00%) instructions in affected programs: 1353 -> 1317 (-2.66%) GAINED: 124 LOST: 6 v2: fix trailing whitespace, split the last patch in two Connor Abbott (4): ra: cleanup the public API ra: make the p, q test more efficient ra: consider all spillable nodes for spilling ra: optimistically color only one node at a time .../drivers/r300/compiler/radeon_pair_regalloc.c | 2 +- src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 2 +- .../drivers/dri/i965/brw_vec4_reg_allocate.cpp | 2 +- src/mesa/program/register_allocate.c | 146 ++++++++------------- src/mesa/program/register_allocate.h | 5 +- 5 files changed, 60 insertions(+), 97 deletions(-) -- 1.9.3 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
