---
src/mesa/drivers/dri/i965/brw_context.h | 2 ++
src/mesa/drivers/dri/i965/brw_vec4.cpp | 6 ++++--
src/mesa/drivers/dri/i965/brw_vec4.h | 10 ++++++----
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 7 ++++---
src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp | 6 ++++--
src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp | 8 +++++---
6 files changed, 25 insertions(+), 14 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 18149b5..08760de 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -598,6 +598,8 @@ struct brw_vec4_prog_data {
* is the size of the URB entry used for output.
*/
GLuint urb_entry_size;
+
+ bool has_control_flow;
};
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index daff364..9e68ebc 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -1831,11 +1831,13 @@ brw_vs_emit(struct brw_context *brw,
if (brw->gen >= 8) {
gen8_vec4_generator g(brw, prog, &c->vp->program.Base, &prog_data->base,
mem_ctx, INTEL_DEBUG & DEBUG_VS);
- assembly = g.generate_assembly(&v.instructions, final_assembly_size);
+ assembly = g.generate_assembly(&v.instructions, final_assembly_size,
+ &prog_data->base.has_control_flow);
} else {
vec4_generator g(brw, prog, &c->vp->program.Base, &prog_data->base,
mem_ctx, INTEL_DEBUG & DEBUG_VS);
- assembly = g.generate_assembly(&v.instructions, final_assembly_size);
+ assembly = g.generate_assembly(&v.instructions, final_assembly_size,
+ &prog_data->base.has_control_flow);
}
if (unlikely(brw->perf_debug) && shader) {
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
b/src/mesa/drivers/dri/i965/brw_vec4.h
index ebe707f..e895659 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -647,10 +647,11 @@ public:
bool debug_flag);
~vec4_generator();
- const unsigned *generate_assembly(exec_list *insts, unsigned *asm_size);
+ const unsigned *generate_assembly(exec_list *insts, unsigned *asm_size,
+ bool *has_control_flow);
private:
- void generate_code(exec_list *instructions);
+ void generate_code(exec_list *instructions, bool *has_control_flow);
void generate_vec4_instruction(vec4_instruction *inst,
struct brw_reg dst,
struct brw_reg *src);
@@ -748,10 +749,11 @@ public:
bool debug_flag);
~gen8_vec4_generator();
- const unsigned *generate_assembly(exec_list *insts, unsigned *asm_size);
+ const unsigned *generate_assembly(exec_list *insts, unsigned *asm_size,
+ bool *has_control_flow);
private:
- void generate_code(exec_list *instructions);
+ void generate_code(exec_list *instructions, bool *has_control_flow);
void generate_vec4_instruction(vec4_instruction *inst,
struct brw_reg dst,
struct brw_reg *src);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index bcacde9..ba8d26d 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -1260,7 +1260,7 @@
vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
}
void
-vec4_generator::generate_code(exec_list *instructions)
+vec4_generator::generate_code(exec_list *instructions, bool *has_control_flow)
{
int last_native_insn_offset = 0;
const char *last_annotation_string = NULL;
@@ -1359,10 +1359,11 @@ vec4_generator::generate_code(exec_list *instructions)
const unsigned *
vec4_generator::generate_assembly(exec_list *instructions,
- unsigned *assembly_size)
+ unsigned *assembly_size,
+ bool *has_control_flow)
{
brw_set_access_mode(p, BRW_ALIGN_16);
- generate_code(instructions);
+ generate_code(instructions, has_control_flow);
return brw_get_program(p, assembly_size);
}
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
index 1321a94..428ed60 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
@@ -570,11 +570,13 @@ generate_assembly(struct brw_context *brw,
if (brw->gen >= 8) {
gen8_vec4_generator g(brw, shader_prog, prog, prog_data, mem_ctx,
INTEL_DEBUG & DEBUG_GS);
- return g.generate_assembly(instructions, final_assembly_size);
+ return g.generate_assembly(instructions, final_assembly_size,
+ &prog_data->has_control_flow);
} else {
vec4_generator g(brw, shader_prog, prog, prog_data, mem_ctx,
INTEL_DEBUG & DEBUG_GS);
- return g.generate_assembly(instructions, final_assembly_size);
+ return g.generate_assembly(instructions, final_assembly_size,
+ &prog_data->has_control_flow);
}
}
diff --git a/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
b/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
index b854db5..222e81a 100644
--- a/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
@@ -793,7 +793,8 @@
gen8_vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
}
void
-gen8_vec4_generator::generate_code(exec_list *instructions)
+gen8_vec4_generator::generate_code(exec_list *instructions,
+ bool *has_control_flow)
{
int last_native_inst_offset = 0;
const char *last_annotation_string = NULL;
@@ -886,11 +887,12 @@ gen8_vec4_generator::generate_code(exec_list
*instructions)
const unsigned *
gen8_vec4_generator::generate_assembly(exec_list *instructions,
- unsigned *assembly_size)
+ unsigned *assembly_size,
+ bool *has_control_flow)
{
default_state.access_mode = BRW_ALIGN_16;
default_state.exec_size = BRW_EXECUTE_8;
- generate_code(instructions);
+ generate_code(instructions, has_control_flow);
*assembly_size = next_inst_offset;
return (const unsigned *) store;
}
--
1.8.3.2
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