On 05/06/2014 12:59 PM, Matt Turner wrote:
> ---
> Noticed by inspection. Not tested.
>
> It looks like this would have messed up the scratch space base pointer.
>
> src/mesa/drivers/dri/i965/gen8_ps_state.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c
> b/src/mesa/drivers/dri/i965/gen8_ps_state.c
> index 7d8f954..3006a0e 100644
> --- a/src/mesa/drivers/dri/i965/gen8_ps_state.c
> +++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c
> @@ -134,7 +134,7 @@ static void
> upload_ps_state(struct brw_context *brw)
> {
> struct gl_context *ctx = &brw->ctx;
> - uint32_t dw3 = 0, dw6 = 0, dw7 = 0;
> + uint32_t dw2 = 0, dw3 = 0, dw6 = 0, dw7 = 0;
>
> /* CACHE_NEW_SAMPLER */
> BEGIN_BATCH(2);
> @@ -149,7 +149,7 @@ upload_ps_state(struct brw_context *brw)
> * incorrect for subspans where some of the pixels are unlit. We believe
> * the bit just didn't take effect in previous generations.
> */
> - dw3 |= GEN7_PS_VECTOR_MASK_ENABLE;
> + dw2 |= GEN7_PS_VECTOR_MASK_ENABLE;
>
> /* CACHE_NEW_SAMPLER */
> dw3 |=
> @@ -229,7 +229,7 @@ upload_ps_state(struct brw_context *brw)
> OUT_BATCH(brw->wm.base.prog_offset +
> brw->wm.prog_data->prog_offset_16);
> else
> OUT_BATCH(brw->wm.base.prog_offset);
> - OUT_BATCH(0);
> + OUT_BATCH(dw2);
> OUT_BATCH(dw3);
> if (brw->wm.prog_data->total_scratch) {
> OUT_RELOC64(brw->wm.base.scratch_bo,NAK. I don't know what docs you're looking at, but the latest ones: DW0 - header, opcode, length DW1, DW2 - kernel start pointer 0 DW3. has bit 30, "Vector Mask Enable." I'm pretty sure the code is correct as is. --Ken
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