On Mon, Feb 24, 2014 at 06:02:23PM +0900, Michel Dänzer wrote:
> From: Michel Dänzer <michel.daen...@amd.com>
>
> Signed-off-by: Michel Dänzer <michel.daen...@amd.com>
> ---
> lib/Target/R600/SILowerControlFlow.cpp | 50
> ++++++++++++++++++++++------------
> test/CodeGen/R600/llvm.AMDGPU.kill.ll | 18 ++++++++++++
> 2 files changed, 50 insertions(+), 18 deletions(-)
> create mode 100644 test/CodeGen/R600/llvm.AMDGPU.kill.ll
>
> diff --git a/lib/Target/R600/SILowerControlFlow.cpp
> b/lib/Target/R600/SILowerControlFlow.cpp
> index f6f9016..1fe620b 100644
> --- a/lib/Target/R600/SILowerControlFlow.cpp
> +++ b/lib/Target/R600/SILowerControlFlow.cpp
> @@ -151,22 +151,34 @@ void SILowerControlFlowPass::SkipIfDead(MachineInstr
> &MI) {
> MachineBasicBlock::iterator Insert = &MI;
> ++Insert;
>
> - // If the exec mask is non-zero, skip the next two instructions
> - BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
> - .addImm(3)
> - .addReg(AMDGPU::EXEC);
> -
> - // Exec mask is zero: Export to NULL target...
> - BuildMI(MBB, Insert, DL, TII->get(AMDGPU::EXP))
> - .addImm(0)
> - .addImm(0x09) // V_008DFC_SQ_EXP_NULL
> - .addImm(0)
> - .addImm(1)
> - .addImm(1)
> - .addReg(AMDGPU::VGPR0)
> - .addReg(AMDGPU::VGPR0)
> - .addReg(AMDGPU::VGPR0)
> - .addReg(AMDGPU::VGPR0);
> + if (MBB.getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType ==
> + ShaderType::PIXEL) {
> + // If the exec mask is non-zero, skip the next two instructions
> + BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
> + .addImm(3)
> + .addReg(AMDGPU::EXEC);
> +
> + // Exec mask is zero: Export to NULL target...
> + BuildMI(MBB, Insert, DL, TII->get(AMDGPU::EXP))
> + .addImm(0)
> + .addImm(0x09) // V_008DFC_SQ_EXP_NULL
> + .addImm(0)
> + .addImm(1)
> + .addImm(1)
> + .addReg(AMDGPU::VGPR0)
> + .addReg(AMDGPU::VGPR0)
> + .addReg(AMDGPU::VGPR0)
> + .addReg(AMDGPU::VGPR0);
> + } else {
> + // If the exec mask is non-zero, skip the next two instructions
> + BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
> + .addImm(2)
> + .addReg(AMDGPU::EXEC);
> +
> + // Signal GS done
> + BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_SENDMSG))
> + .addImm(3);
> + }
>
> // ... and terminate wavefront
> BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM));
> @@ -293,9 +305,11 @@ void SILowerControlFlowPass::Kill(MachineInstr &MI) {
> MachineBasicBlock &MBB = *MI.getParent();
> DebugLoc DL = MI.getDebugLoc();
>
> - // Kill is only allowed in pixel shaders
> + // Kill is only allowed in pixel / geometry shaders
> assert(MBB.getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType ==
> - ShaderType::PIXEL);
> + ShaderType::PIXEL ||
> + MBB.getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType ==
> + ShaderType::GEOMETRY);
>
> // Clear this pixel from the exec mask if the operand is negative
> BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMPX_LE_F32_e32), AMDGPU::VCC)
> diff --git a/test/CodeGen/R600/llvm.AMDGPU.kill.ll
> b/test/CodeGen/R600/llvm.AMDGPU.kill.ll
> new file mode 100644
> index 0000000..0abe694
> --- /dev/null
> +++ b/test/CodeGen/R600/llvm.AMDGPU.kill.ll
> @@ -0,0 +1,18 @@
> +; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck
> --check-prefix=SI-CHECK %s
> +
> +; SI-LABEL: @kill_gs
Since your prefix is SI-CHECK, this would need to be SI-CHECK-LABEL.
With that fix,
Reviewed-by: Tom Stellard <thomas.stell...@amd.com>
> +; SI-CHECK: V_CMPX_LE_F32
> +
> +define void @kill_gs() #0 {
> +main_body:
> + %0 = icmp ule i32 0, 3
> + %1 = select i1 %0, float 1.000000e+00, float -1.000000e+00
> + call void @llvm.AMDGPU.kill(float %1)
> + ret void
> +}
> +
> +declare void @llvm.AMDGPU.kill(float)
> +
> +attributes #0 = { "ShaderType"="2" }
> +
> +!0 = metadata !{metadata !"const", null, i32 1}
> --
> 1.9.0
>
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