From: Marek Olšák <marek.ol...@amd.com>
We can just use the base address register instead.
---
src/gallium/drivers/r600/evergreen_state.c | 6 ++----
src/gallium/drivers/r600/r600_state.c | 6 ++----
src/gallium/drivers/radeon/r600_pipe_common.h | 2 --
3 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 82baa0f..3dd576b 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1694,11 +1694,9 @@ static void evergreen_init_depth_surface(struct
r600_context *rctx,
S_028044_FORMAT(V_028044_STENCIL_8);
}
- surf->htile_enabled = 0;
/* use htile only for first level */
if (rtex->htile_buffer && !level) {
uint64_t va = r600_resource_va(&rctx->screen->b.b,
&rtex->htile_buffer->b.b);
- surf->htile_enabled = 1;
surf->db_htile_data_base = va >> 8;
surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
S_028ABC_HTILE_HEIGHT(1) |
@@ -2368,7 +2366,7 @@ static void evergreen_emit_db_state(struct r600_context
*rctx, struct r600_atom
struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
struct r600_db_state *a = (struct r600_db_state*)atom;
- if (a->rsurf && a->rsurf->htile_enabled) {
+ if (a->rsurf && a->rsurf->db_htile_data_base) {
struct r600_texture *rtex = (struct r600_texture
*)a->rsurf->base.texture;
unsigned reloc_idx;
@@ -2409,7 +2407,7 @@ static void evergreen_emit_db_misc_state(struct
r600_context *rctx, struct r600_
*
* Disable hyperz for now if not writing to zbuffer.
*/
- if (rctx->db_state.rsurf && rctx->db_state.rsurf->htile_enabled &&
rctx->zwritemask) {
+ if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_data_base &&
rctx->zwritemask) {
/* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL
*/
db_render_override |=
S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_OFF);
/* This is to fix a lockup when hyperz and alpha test are
enabled at
diff --git a/src/gallium/drivers/r600/r600_state.c
b/src/gallium/drivers/r600/r600_state.c
index 0dfd426..815ed1f 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1530,11 +1530,9 @@ static void r600_init_depth_surface(struct r600_context
*rctx,
default:;
}
- surf->htile_enabled = 0;
/* use htile only for first level */
if (rtex->htile_buffer && !level) {
uint64_t va = r600_resource_va(&rctx->screen->b.b,
&rtex->htile_buffer->b.b);
- surf->htile_enabled = 1;
surf->db_htile_data_base = va >> 8;
surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) |
S_028D24_HTILE_HEIGHT(1) |
@@ -1993,7 +1991,7 @@ static void r600_emit_db_state(struct r600_context *rctx,
struct r600_atom *atom
struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
struct r600_db_state *a = (struct r600_db_state*)atom;
- if (a->rsurf && a->rsurf->htile_enabled) {
+ if (a->rsurf && a->rsurf->db_htile_data_base) {
struct r600_texture *rtex = (struct r600_texture
*)a->rsurf->base.texture;
unsigned reloc_idx;
@@ -2023,7 +2021,7 @@ static void r600_emit_db_misc_state(struct r600_context
*rctx, struct r600_atom
}
db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
}
- if (rctx->db_state.rsurf && rctx->db_state.rsurf->htile_enabled) {
+ if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_data_base) {
/* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL
*/
db_render_override |=
S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF);
/* This is to fix a lockup when hyperz and alpha test are
enabled at
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 38c784a..9569c03 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -201,8 +201,6 @@ struct r600_surface {
unsigned db_htile_data_base;
unsigned db_preload_control; /* EG and later */
unsigned pa_su_poly_offset_db_fmt_cntl;
-
- unsigned htile_enabled; /* XXX remove */
};
struct r600_tiling_info {
--
1.8.3.2
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