Note that tile offset calculation is unnecessary for hiz as it does not have a shader that would use them nor does the hiz execution update the surface state table for destination - it configures only the depth surface which is handled separately.
No regressions on IVB and SNB. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_blorp.cpp | 10 ++++++---- src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 2 ++ src/mesa/drivers/dri/i965/gen6_blorp.cpp | 4 ++-- src/mesa/drivers/dri/i965/gen7_blorp.cpp | 2 +- 4 files changed, 11 insertions(+), 7 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp index 5cff9b4..355552d 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp @@ -192,14 +192,16 @@ brw_blorp_params::configure_miplevel_offsets() { uint32_t src_tile_orig_space_x = 0; uint32_t src_tile_orig_space_y = 0; - uint32_t dst_tile_orig_space_x = 0; - uint32_t dst_tile_orig_space_y = 0; + uint32_t dst_tile_orig_space_x; + uint32_t dst_tile_orig_space_y; + dst.compute_tile_offsets(&dst.tile_x, &dst.tile_y); if (dst.map_stencil_as_y_tiled) { - dst.compute_tile_offsets(&dst.tile_x, &dst.tile_y); - dst_tile_orig_space_x = dst.tile_x / 2; dst_tile_orig_space_y = dst.tile_y * 2; + } else { + dst_tile_orig_space_x = dst.tile_x; + dst_tile_orig_space_y = dst.tile_y; } if (src.map_stencil_as_y_tiled) { diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp index 94672e0..701561b 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp @@ -191,6 +191,7 @@ brw_blorp_clear_params::brw_blorp_clear_params(struct brw_context *brw, struct intel_renderbuffer *irb = intel_renderbuffer(rb); dst.set(brw, irb->mt, irb->mt_level, layer, true); + dst.compute_tile_offsets(&dst.tile_x, &dst.tile_y); /* Override the surface format according to the context's sRGB rules. */ mesa_format format = _mesa_get_render_format(ctx, irb->mt->format); @@ -362,6 +363,7 @@ brw_blorp_rt_resolve_params::brw_blorp_rt_resolve_params( struct intel_mipmap_tree *mt) { dst.set(brw, mt, 0 /* level */, 0 /* layer */, true); + dst.compute_tile_offsets(&dst.tile_x, &dst.tile_y); /* From the Ivy Bridge PRM, Vol2 Part1 11.9 "Render Target Resolve": * diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp index e5b3d3c..c89ec86 100644 --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp @@ -394,7 +394,7 @@ gen6_blorp_emit_surface_state(struct brw_context *brw, /* When the tile offsets are handled by the blorp program directly the * dimensions of the surface need to be updated to allow full access. */ - if (surface->map_stencil_as_y_tiled) { + if (surface->map_stencil_as_y_tiled || ¶ms->dst == surface) { width += surface->tile_x; height += surface->tile_y; } @@ -416,7 +416,7 @@ gen6_blorp_emit_surface_state(struct brw_context *brw, surf[5] = (surface->mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0); - if (!surface->map_stencil_as_y_tiled) { + if (!surface->map_stencil_as_y_tiled && ¶ms->dst != surface) { uint32_t tile_x, tile_y; surface->compute_tile_offsets(&tile_x, &tile_y); diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp index 337b7b9..8488e26 100644 --- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp @@ -181,7 +181,7 @@ gen7_blorp_emit_surface_state(struct brw_context *brw, /* When the tile offsets are handled by the blorp program directly the * dimensions of the surface need to be updated to allow full access. */ - if (surface->map_stencil_as_y_tiled) { + if (surface->map_stencil_as_y_tiled || is_render_target) { width += surface->tile_x; height += surface->tile_y; } else { -- 1.8.3.1 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev