On 02/04/2014 09:08 PM, Kenneth Graunke wrote:
> According to the latest documentation, any PIPE_CONTROL with the
> "Command Streamer Stall" bit set must also have another bit set,
> with five different options:
>
> - Render Target Cache Flush
> - Depth Cache Flush
> - Stall at Pixel Scoreboard
> - Post-Sync Operation
> - Depth Stall
>
> I chose "Stall at Pixel Scoreboard" since we've used it effectively
> in the past, but the choice is fairly arbitrary.
It looks like some (but not all) of the callers of
brw_emit_pipe_control_flush already have one or more of these flags set
when PIPE_CONTROL_CS_STALL is set. Should we only set
PIPE_CONTROL_STALL_AT_SCOREBOARD if one of the other flags isn't already
set?
> Implementing this in the PIPE_CONTROL emit helpers ensures that the
> workaround will always take effect when it ought to.
>
> Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
> ---
> src/mesa/drivers/dri/i965/intel_batchbuffer.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> index fbbd527..719b026 100644
> --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> @@ -441,6 +441,10 @@ void
> brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags)
> {
> if (brw->gen >= 8) {
> + /* Workarounds */
> + if (flags & PIPE_CONTROL_CS_STALL)
> + flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
> +
> BEGIN_BATCH(6);
> OUT_BATCH(_3DSTATE_PIPE_CONTROL | (6 - 2));
> OUT_BATCH(flags);
> @@ -481,6 +485,10 @@ brw_emit_pipe_control_write(struct brw_context *brw,
> uint32_t flags,
> uint32_t imm_lower, uint32_t imm_upper)
> {
> if (brw->gen >= 8) {
> + /* Workarounds */
> + if (flags & PIPE_CONTROL_CS_STALL)
> + flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
> +
> BEGIN_BATCH(6);
> OUT_BATCH(_3DSTATE_PIPE_CONTROL | (6 - 2));
> OUT_BATCH(flags);
>
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