We never set it on previous generations, but I had to set it in
3DSTATE_PS for correct behavior. For symmetry, I set it in 3DSTATE_VS
as well, but there's no actual need to do so. Piglit works fine either
way. The documentation also remarks that there should never be a need
to program this.
Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/gen8_vs_state.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/gen8_vs_state.c
b/src/mesa/drivers/dri/i965/gen8_vs_state.c
index 65a62f3..02a0176 100644
--- a/src/mesa/drivers/dri/i965/gen8_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_vs_state.c
@@ -87,7 +87,7 @@ upload_vs_state(struct brw_context *brw)
OUT_BATCH(_3DSTATE_VS << 16 | (9 - 2));
OUT_BATCH(stage_state->prog_offset);
OUT_BATCH(0);
- OUT_BATCH(GEN6_VS_VECTOR_MASK_ENABLE | floating_point_mode |
+ OUT_BATCH(floating_point_mode |
((ALIGN(stage_state->sampler_count, 4) / 4) <<
GEN6_VS_SAMPLER_COUNT_SHIFT) |
((prog_data->base.binding_table.size_bytes / 4) <<
--
1.8.4.2
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