On 28 January 2014 11:22, Jordan Justen <jordan.l.jus...@intel.com> wrote:
> Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
> ---
> src/mesa/drivers/dri/i965/brw_defines.h | 5 +++++
> src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp | 24
> ++++++++++++++++++++---
> 2 files changed, 26 insertions(+), 3 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
> b/src/mesa/drivers/dri/i965/brw_defines.h
> index 7f4cd10..5fe1aba 100644
> --- a/src/mesa/drivers/dri/i965/brw_defines.h
> +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> @@ -1500,6 +1500,11 @@ enum brw_message_target {
> # define BRW_GS_EDGE_INDICATOR_0 (1 << 8)
> # define BRW_GS_EDGE_INDICATOR_1 (1 << 9)
>
> +/* GS Thread Payload
> + */
> +/* R0 */
> +# define GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT 27
> +
> /* 3DSTATE_GS "Output Vertex Size" has an effective maximum of 62. It's
> * counted in multiples of 16 bytes.
> */
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
> b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
> index 40743cc..12e137c 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
> @@ -51,9 +51,27 @@ vec4_gs_visitor::vec4_gs_visitor(struct brw_context
> *brw,
> dst_reg *
> vec4_gs_visitor::make_reg_for_system_value(ir_variable *ir)
> {
> - /* Geometry shaders don't use any system values. */
> - assert(!"Unreached");
> - return NULL;
> + dst_reg *reg;
> + src_reg r0(retype(brw_vec4_grf(0, 0), BRW_REGISTER_TYPE_UD));
> +
> + switch (ir->data.location) {
> + case SYSTEM_VALUE_INVOCATION_ID:
> + this->current_annotation = "initialize gl_InvocationID";
> +
> + reg = new(mem_ctx) dst_reg(this, ir->type);
> +
> + /* Copy and shift gen7 instance id from R0 into the
> + * gl_InvocationID register.
> + */
> + emit(SHR(*reg, src_reg(r0),
> + (uint32_t) GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT));
> + break;
> + default:
> + assert(!"not reached");
> + break;
> + }
> +
> + return reg;
> }
>
This would do what you want if invocation ID 0 was delivered in the upper
bits of R0.0 and invocation ID 1 was delivered in the upper bits of R0.4.
But that's not the case. They are delivered in R0.0 and R0.1
respectively. I think you need to generate this instruction:
SHR (8) dst<1> R0<1;4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
Note that this instruction requires ALIGN1 mode and a goofy register
region, so you can't generate it directly from the visitor; what you'll
have to do instead is create a new opcode to do it. If you want to see
examples where we've done similar things, grep for
GS_OPCODE_SET_WRITE_OFFSET, GS_OPCODE_SET_VERTEX_COUNT,
GS_OPCODE_SET_DWORD_2_IMMED, GS_OPCODE_PREPARE_CHANNEL_MASKS, or
GS_OPCODE_SET_CHANNEL_MASKS.
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