Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
---
src/mesa/drivers/dri/i965/brw_context.h | 2 ++
src/mesa/drivers/dri/i965/brw_defines.h | 5 +++++
src/mesa/drivers/dri/i965/brw_vec4_gs.c | 3 +++
src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp | 17 +++++++++++++++++
4 files changed, 27 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 42d40e6..7c95898 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -639,6 +639,8 @@ struct brw_gs_prog_data
bool include_primitive_id;
+ bool invocation_id_read;
+
/**
* True if the thread should be dispatched in DUAL_INSTANCE mode, false if
* it should be dispatched in DUAL_OBJECT mode.
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 7f4cd10..5fe1aba 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1500,6 +1500,11 @@ enum brw_message_target {
# define BRW_GS_EDGE_INDICATOR_0 (1 << 8)
# define BRW_GS_EDGE_INDICATOR_1 (1 << 9)
+/* GS Thread Payload
+ */
+/* R0 */
+# define GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT 27
+
/* 3DSTATE_GS "Output Vertex Size" has an effective maximum of 62. It's
* counted in multiples of 16 bytes.
*/
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs.c
b/src/mesa/drivers/dri/i965/brw_vec4_gs.c
index abc181b..fbef5e3 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_vec4_gs.c
@@ -48,6 +48,9 @@ do_gs_prog(struct brw_context *brw,
c.prog_data.include_primitive_id =
(gp->program.Base.InputsRead & VARYING_BIT_PRIMITIVE_ID) != 0;
+ c.prog_data.invocation_id_read =
+ (gp->program.Base.InputsRead & VARYING_BIT_INVOCATION_ID) != 0;
+
/* Allocate the references to the uniforms that will end up in the
* prog_data associated with the compiled program, and which will be freed
* by the state cache.
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
index 40743cc..0593e66 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
@@ -117,6 +117,10 @@ vec4_gs_visitor::setup_payload()
if (c->prog_data.include_primitive_id)
attribute_map[VARYING_SLOT_PRIMITIVE_ID] = attributes_per_reg * reg++;
+ /* If the shader uses gl_InvocationID, allocate a register. */
+ if (c->prog_data.invocation_id_read)
+ attribute_map[VARYING_SLOT_INVOCATION_ID] = attributes_per_reg * reg++;
+
reg = setup_uniforms(reg);
reg = setup_varying_inputs(reg, attribute_map, attributes_per_reg);
@@ -192,6 +196,19 @@ vec4_gs_visitor::emit_prolog()
}
}
+ /* If the shader uses gl_InvocationID, then move the value into the
+ * allocated register.
+ */
+ if (c->prog_data.invocation_id_read) {
+ dst_reg dst(ATTR, VARYING_SLOT_INVOCATION_ID);
+
+ /* Initialize the gl_InstanceID register from R0. */
+ this->current_annotation = "initialize gl_InvocationID";
+ inst = emit(SHR(dst, src_reg(r0),
+ (uint32_t) GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT));
+ inst->force_writemask_all = true;
+ }
+
this->current_annotation = NULL;
}
--
1.8.5.3
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