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On 01/21/2014 08:07 AM, Topi Pohjolainen wrote:
> No known bugs fixed but this is now in line with fs-generator. No
> regresssions on IVB.
>
> CC: Paul Berry <stereotype...@gmail.com> Signed-off-by: Topi
> Pohjolainen <topi.pohjolai...@intel.com> ---
> src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 46
> ++++++++++++++--------
> .../drivers/dri/i965/test_blorp_blit_eu_gen.cpp | 24
> +++++------ 2 files changed, 42 insertions(+), 28 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
> b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp index
> e2c2562..3b92c56 100644 ---
> a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp +++
> b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp @@ -658,6 +658,11 @@
> private: const sampler_message_arg *args, int num_args); void
> render_target_write();
>
> + void emit_lrp(const struct brw_reg &dst, +
> const struct brw_reg &src1, + const struct brw_reg
> &src2, + const struct brw_reg &src3); + /** *
> Base-2 logarithm of the maximum number of samples that can be
> blended. */ @@ -1656,6 +1661,21 @@
> brw_blorp_blit_program::manual_blend_average(unsigned num_samples)
> }
>
> void +brw_blorp_blit_program::emit_lrp(const struct brw_reg &dst, +
> const struct brw_reg &src1, + const
> struct brw_reg &src2, + const
> struct brw_reg &src3) +{ + brw_set_access_mode(&func,
> BRW_ALIGN_16); + brw_set_compression_control(&func,
> BRW_COMPRESSION_NONE); + brw_LRP(&func, dst, src1, src2, src3); +
> brw_set_compression_control(&func, BRW_COMPRESSION_2NDHALF); +
> brw_LRP(&func, sechalf(dst), sechalf(src1), sechalf(src2),
> sechalf(src3)); + brw_set_compression_control(&func,
> BRW_COMPRESSION_COMPRESSED); + brw_set_access_mode(&func,
> BRW_ALIGN_1); +}
Series is also:
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
As a future small performance improvement, three-source opcodes like
LRP don't actually need to be split into two SIMD8 halves on Haswell
and later. Would be great to do that too.
Thanks for your work on this, Topi!
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