Effectively only the mask control bit gets altered for the single
addition in question and hence there is no real need to use a
fresh state control level for it -- that is more useful when
multiple intructions share the same mask and compression settings.
This is a preparation step for removing the explicit compression
control modifiers in the blit compiler. After this patch there
are no nested state control levels making the constant nature of
the compression settings more apparent.
No regressions on IVB (piglit quick + unit tests).
Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 112a307..4d62411 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1407,10 +1407,7 @@ brw_blorp_blit_program::kill_if_outside_dst_rect()
brw_CMP(&func, null32, BRW_CONDITIONAL_L, Y, dst_y1);
brw_set_predicate_control(&func, BRW_PREDICATE_NONE);
- brw_push_insn_state(&func);
- brw_set_mask_control(&func, BRW_MASK_DISABLE);
- brw_AND(&func, g1, f0, g1);
- brw_pop_insn_state(&func);
+ brw_AND(&func, g1, f0, g1)->header.mask_control = BRW_MASK_DISABLE;
}
/**
--
1.8.3.1
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