Unfortunately the unit tests need to be patched as well. This is
because the direct eu-emitter only patches jump counters for
if-else (see patch_IF_ELSE()) while the fs_generator patches the
endif as well (see brw_set_uip_jip()).
No regressions on IVB (piglit quick + unit tests).
Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp | 118 ++++++++-------------
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h | 63 +++++------
.../drivers/dri/i965/test_blorp_blit_eu_gen.cpp | 6 +-
3 files changed, 83 insertions(+), 104 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
index dcfd82b..46033ba 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
@@ -26,24 +26,10 @@
#include "brw_blorp.h"
brw_blorp_eu_emitter::brw_blorp_eu_emitter(struct brw_context *brw)
- : mem_ctx(ralloc_context(NULL))
+ : mem_ctx(ralloc_context(NULL)), c(rzalloc(mem_ctx, struct brw_wm_compile)),
+ generator(brw, c, NULL, NULL, false)
{
- brw_init_compile(brw, &func, mem_ctx);
-
- /*
- * By default everything is emitted as 16-wide with only a few expections
- * handled explicitly either here in the compiler or by one of the specific
- * code emission calls.
- * It should be also noted that here in this file any alterations of the
- * compression control settings are only used to affect the execution size
- * of the instructions. The instruction template used to initialise all the
- * instructions is effectively not altered -- the value stays at zero
- * representing either GEN6_COMPRESSION_1Q or GEN6_COMPRESSION_1H depending
- * on the context.
- * If any other settings are used in the instruction headers, they are set
- * elsewhere by the individual code emission calls.
- */
- brw_set_compression_control(&func, BRW_COMPRESSION_COMPRESSED);
+ generator.no_2nd_half_ctrl = true;
}
brw_blorp_eu_emitter::~brw_blorp_eu_emitter()
@@ -54,13 +40,18 @@ brw_blorp_eu_emitter::~brw_blorp_eu_emitter()
const unsigned *
brw_blorp_eu_emitter::get_program(unsigned *program_size, FILE *dump_file)
{
+ const unsigned *res;
+
if (unlikely(INTEL_DEBUG & DEBUG_BLORP)) {
printf("Native code for BLORP blit:\n");
- brw_dump_compile(&func, dump_file, 0, func.next_insn_offset);
+ res = generator.generate_assembly(NULL, &insts, program_size, true,
+ dump_file);
printf("\n");
+ } else {
+ res = generator.generate_assembly(NULL, &insts, program_size);
}
- return brw_get_program(&func, program_size);
+ return res;
}
/**
@@ -78,15 +69,15 @@ brw_blorp_eu_emitter::emit_kill_if_outside_rect(const
struct brw_reg &x,
{
struct brw_reg f0 = brw_flag_reg(0, 0);
struct brw_reg g1 = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
- struct brw_reg null32 = vec16(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
- brw_CMP(&func, null32, BRW_CONDITIONAL_GE, x, dst_x0);
- brw_CMP(&func, null32, BRW_CONDITIONAL_GE, y, dst_y0);
- brw_CMP(&func, null32, BRW_CONDITIONAL_L, x, dst_x1);
- brw_CMP(&func, null32, BRW_CONDITIONAL_L, y, dst_y1);
+ emit_cmp(BRW_CONDITIONAL_GE, x, dst_x0);
+ emit_cmp(BRW_CONDITIONAL_GE, y, dst_y0)->predicate = BRW_PREDICATE_NORMAL;
+ emit_cmp(BRW_CONDITIONAL_L, x, dst_x1)->predicate = BRW_PREDICATE_NORMAL;
+ emit_cmp(BRW_CONDITIONAL_L, y, dst_y1)->predicate = BRW_PREDICATE_NORMAL;
- brw_set_predicate_control(&func, BRW_PREDICATE_NONE);
- brw_AND(&func, g1, f0, g1)->header.mask_control = BRW_MASK_DISABLE;
+ fs_inst *inst = new (mem_ctx) fs_inst(BRW_OPCODE_AND, g1, f0, g1);
+ inst->force_writemask_all = true;
+ insts.push_tail(inst);
}
void
@@ -95,40 +86,14 @@ brw_blorp_eu_emitter::emit_texture_lookup(const struct
brw_reg &dst,
unsigned base_mrf,
unsigned msg_length)
{
- unsigned msg_type;
-
- switch (op) {
- case SHADER_OPCODE_TEX:
- msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
- break;
- case SHADER_OPCODE_TXF:
- msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
- break;
- case SHADER_OPCODE_TXF_CMS:
- msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
- break;
- case SHADER_OPCODE_TXF_UMS:
- msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
- break;
- case SHADER_OPCODE_TXF_MCS:
- msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
- break;
- default:
- assert(!"Unsupported texture lookup operation");
- }
+ fs_inst *inst = new (mem_ctx) fs_inst(op, dst, brw_message_reg(base_mrf));
+
+ inst->base_mrf = base_mrf;
+ inst->mlen = msg_length;
+ inst->sampler = 0;
+ inst->header_present = false;
- brw_SAMPLE(&func,
- retype(dst, BRW_REGISTER_TYPE_UW) /* dest */,
- base_mrf /* msg_reg_nr */,
- brw_message_reg(base_mrf) /* src0 */,
- BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX,
- 0 /* sampler */,
- msg_type,
- 8 /* response_length. TODO: should be smaller for non-RGBA
formats? */,
- msg_length,
- 0 /* header_present */,
- BRW_SAMPLER_SIMD_MODE_SIMD16,
- BRW_SAMPLER_RETURN_FORMAT_FLOAT32);
+ insts.push_tail(inst);
}
void
@@ -137,16 +102,14 @@ brw_blorp_eu_emitter::emit_render_target_write(const
struct brw_reg &src0,
unsigned msg_length,
bool use_header)
{
- brw_fb_WRITE(&func,
- 16 /* dispatch_width */,
- msg_reg_nr,
- src0,
- BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
- BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX,
- msg_length,
- 0 /* response_length */,
- true /* eot */,
- use_header);
+ fs_inst *inst = new (mem_ctx) fs_inst(FS_OPCODE_BLORP_FB_WRITE);
+
+ inst->src[0] = src0;
+ inst->base_mrf = msg_reg_nr;
+ inst->mlen = msg_length;
+ inst->header_present = use_header;
+
+ insts.push_tail(inst);
}
void
@@ -156,7 +119,20 @@ brw_blorp_eu_emitter::emit_combine(unsigned
texture_data_type,
const struct brw_reg &src_2)
{
if (texture_data_type == BRW_REGISTER_TYPE_F)
- brw_ADD(&func, dst, src_1, src_2);
+ insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_ADD, dst, src_1,
src_2));
else
- brw_AVG(&func, dst, src_1, src_2);
+ insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_AVG, dst, src_1,
src_2));
}
+
+fs_inst *
+brw_blorp_eu_emitter::emit_cmp(int op,
+ const struct brw_reg &x,
+ const struct brw_reg &y)
+{
+ fs_inst *cmp = new (mem_ctx) fs_inst(BRW_OPCODE_CMP,
+ vec16(brw_null_reg()), x, y);
+ cmp->conditional_mod = op;
+ insts.push_tail(cmp);
+ return cmp;
+}
+
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h
b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h
index 3f2301c..ccb72f1 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h
@@ -25,7 +25,7 @@
#define BRW_BLORP_BLIT_EU_H
#include "brw_context.h"
-#include "brw_eu.h"
+#include "brw_fs.h"
class brw_blorp_eu_emitter
{
@@ -63,9 +63,11 @@ protected:
const struct brw_reg &dst,
const struct brw_reg &src)
{
- brw_CMP(&func, vec16(brw_null_reg()), op, x, y);
- brw_MOV(&func, dst, src);
- brw_set_predicate_control(&func, BRW_PREDICATE_NONE);
+ emit_cmp(op, x, y);
+
+ fs_inst *mv = new (mem_ctx) fs_inst(BRW_OPCODE_MOV, dst, src);
+ mv->predicate = BRW_PREDICATE_NORMAL;
+ insts.push_tail(mv);
}
inline void emit_if_eq_mov(const struct brw_reg &x, unsigned y,
@@ -79,109 +81,110 @@ protected:
const struct brw_reg &src2,
const struct brw_reg &src3)
{
- brw_set_access_mode(&func, BRW_ALIGN_16);
- brw_set_compression_control(&func, BRW_COMPRESSION_NONE);
- brw_LRP(&func, dst, src1, src2, src3);
- brw_LRP(&func, sechalf(dst), sechalf(src1), sechalf(src2),
sechalf(src3));
- brw_set_compression_control(&func, BRW_COMPRESSION_COMPRESSED);
- brw_set_access_mode(&func, BRW_ALIGN_1);
+ insts.push_tail(
+ new (mem_ctx) fs_inst(BRW_OPCODE_LRP, dst, src1, src2, src3));
}
inline void emit_mov(const struct brw_reg& dst, const struct brw_reg& src)
{
- brw_MOV(&func, dst, src);
+ insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_MOV, dst, src));
}
inline void emit_mov_8(const struct brw_reg& dst, const struct brw_reg& src)
{
- brw_set_compression_control(&func, BRW_COMPRESSION_NONE);
- emit_mov(dst, src);
- brw_set_compression_control(&func, BRW_COMPRESSION_COMPRESSED);
+ fs_inst *mv = new (mem_ctx) fs_inst(BRW_OPCODE_MOV, dst, src);
+ mv->force_uncompressed = true;
+ insts.push_tail(mv);
}
inline void emit_and(const struct brw_reg& dst,
const struct brw_reg& src1,
const struct brw_reg& src2)
{
- brw_AND(&func, dst, src1, src2);
+ insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_AND, dst, src1, src2));
}
inline void emit_add(const struct brw_reg& dst,
const struct brw_reg& src1,
const struct brw_reg& src2)
{
- brw_ADD(&func, dst, src1, src2);
+ insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_ADD, dst, src1, src2));
}
inline void emit_add_8(const struct brw_reg& dst,
const struct brw_reg& src1,
const struct brw_reg& src2)
{
- brw_set_compression_control(&func, BRW_COMPRESSION_NONE);
- emit_add(dst, src1, src2);
- brw_set_compression_control(&func, BRW_COMPRESSION_COMPRESSED);
+ fs_inst *add = new (mem_ctx) fs_inst(BRW_OPCODE_ADD, dst, src1, src2);
+ add->force_uncompressed = true;
+ insts.push_tail(add);
}
inline void emit_mul(const struct brw_reg& dst,
const struct brw_reg& src1,
const struct brw_reg& src2)
{
- brw_MUL(&func, dst, src1, src2);
+ insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_MUL, dst, src1, src2));
}
inline void emit_shr(const struct brw_reg& dst,
const struct brw_reg& src1,
const struct brw_reg& src2)
{
- brw_SHR(&func, dst, src1, src2);
+ insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_SHR, dst, src1, src2));
}
inline void emit_shl(const struct brw_reg& dst,
const struct brw_reg& src1,
const struct brw_reg& src2)
{
- brw_SHL(&func, dst, src1, src2);
+ insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_SHL, dst, src1, src2));
}
inline void emit_or(const struct brw_reg& dst,
const struct brw_reg& src1,
const struct brw_reg& src2)
{
- brw_OR(&func, dst, src1, src2);
+ insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_OR, dst, src1, src2));
}
inline void emit_frc(const struct brw_reg& dst,
const struct brw_reg& src)
{
- brw_FRC(&func, dst, src);
+ insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_FRC, dst, src));
}
inline void emit_rndd(const struct brw_reg& dst,
const struct brw_reg& src)
{
- brw_RNDD(&func, dst, src);
+ insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_RNDD, dst, src));
}
inline void emit_if(int op,
const struct brw_reg &x,
const struct brw_reg &y)
{
- brw_CMP(&func, vec16(brw_null_reg()), op, x, y);
- brw_IF(&func, BRW_EXECUTE_16);
+ emit_cmp(op, x, y);
+ insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_IF));
}
inline void emit_else(void)
{
- brw_ELSE(&func);
+ insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_ELSE));
}
inline void emit_endif(void)
{
- brw_ENDIF(&func);
+ insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_ENDIF));
}
+private:
+ fs_inst *emit_cmp(int op, const struct brw_reg &x, const struct brw_reg &y);
+
void *mem_ctx;
- struct brw_compile func;
+ struct brw_wm_compile *c;
+ exec_list insts;
+ fs_generator generator;
};
#endif /* BRW_BLORP_BLIT_EU_H */
diff --git a/src/mesa/drivers/dri/i965/test_blorp_blit_eu_gen.cpp
b/src/mesa/drivers/dri/i965/test_blorp_blit_eu_gen.cpp
index 8b0cac2..208959a 100644
--- a/src/mesa/drivers/dri/i965/test_blorp_blit_eu_gen.cpp
+++ b/src/mesa/drivers/dri/i965/test_blorp_blit_eu_gen.cpp
@@ -154,7 +154,7 @@ test_gen7_blend_scaled_msaa_8(struct brw_context *brw)
"0x00000340: (+f0) mov(16) g64<1>UD 7D
{ align1 WE_normal 1H };\n"
"0x00000350: cmp.e.f0(16) null g60<8,8,1>UD 7D
{ align1 WE_normal 1H switch };\n"
"0x00000360: (+f0) mov(16) g64<1>UD 1D
{ align1 WE_normal 1H };\n"
- "0x00000370: endif(16) 2 null
0x00000002UD { align1 WE_normal 1H switch };\n"
+ "0x00000370: endif(16) 50 null
0x00000032UD { align1 WE_normal 1H switch };\n"
"0x00000380: mov(16) g60<1>UD g64<8,8,1>UD
{ align1 WE_normal 1H };\n"
"0x00000390: mov(16) g114<1>UD g60<8,8,1>UD
{ align1 WE_normal 1H };\n"
"0x000003a0: mov(16) g116<1>UD g44<8,8,1>UD
{ align1 WE_normal 1H };\n"
@@ -188,7 +188,7 @@ test_gen7_blend_scaled_msaa_8(struct brw_context *brw)
"0x00000550: (+f0) mov(16) g64<1>UD 7D
{ align1 WE_normal 1H };\n"
"0x00000560: cmp.e.f0(16) null g60<8,8,1>UD 7D
{ align1 WE_normal 1H switch };\n"
"0x00000570: (+f0) mov(16) g64<1>UD 1D
{ align1 WE_normal 1H };\n"
- "0x00000580: endif(16) 2 null
0x00000002UD { align1 WE_normal 1H switch };\n"
+ "0x00000580: endif(16) 50 null
0x00000032UD { align1 WE_normal 1H switch };\n"
"0x00000590: mov(16) g60<1>UD g64<8,8,1>UD
{ align1 WE_normal 1H };\n"
"0x000005a0: mov(16) g114<1>UD g60<8,8,1>UD
{ align1 WE_normal 1H };\n"
"0x000005b0: mov(16) g116<1>UD g44<8,8,1>UD
{ align1 WE_normal 1H };\n"
@@ -222,7 +222,7 @@ test_gen7_blend_scaled_msaa_8(struct brw_context *brw)
"0x00000760: (+f0) mov(16) g64<1>UD 7D
{ align1 WE_normal 1H };\n"
"0x00000770: cmp.e.f0(16) null g60<8,8,1>UD 7D
{ align1 WE_normal 1H switch };\n"
"0x00000780: (+f0) mov(16) g64<1>UD 1D
{ align1 WE_normal 1H };\n"
- "0x00000790: endif(16) 2 null
0x00000002UD { align1 WE_normal 1H switch };\n"
+ "0x00000790: endif(16) 50 null
0x00000032UD { align1 WE_normal 1H switch };\n"
"0x000007a0: mov(16) g60<1>UD g64<8,8,1>UD
{ align1 WE_normal 1H };\n"
"0x000007b0: mov(16) g114<1>UD g60<8,8,1>UD
{ align1 WE_normal 1H };\n"
"0x000007c0: mov(16) g116<1>UD g44<8,8,1>UD
{ align1 WE_normal 1H };\n"
--
1.8.3.1
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