"m_" in patch 1 seems a bit odd, but I've nothing better to suggest.
Patch 5 seems like a definite improvement.
Series Reviewed-by: Jordan Justen <jordan.l.jus...@intel.com>
On Tue, Dec 10, 2013 at 2:33 AM, Kenneth Graunke <kenn...@whitecape.org> wrote:
> Broadwell introduces support for Q, UQ, and HF types. It also extends
> DF support to allow immediate values.
>
> Irritatingly, although HF and DF both support immediates, they're
> represented by a different value depending on the register file.
>
> Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
> ---
> src/mesa/drivers/dri/i965/brw_defines.h | 5 +++++
> src/mesa/drivers/dri/i965/brw_eu_emit.c | 10 +++++++++-
> src/mesa/drivers/dri/i965/brw_reg.h | 5 +++++
> 3 files changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
> b/src/mesa/drivers/dri/i965/brw_defines.h
> index 5ee6fb7..dc38ace 100644
> --- a/src/mesa/drivers/dri/i965/brw_defines.h
> +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> @@ -987,14 +987,19 @@ operator|(brw_urb_write_flags x, brw_urb_write_flags y)
> #define BRW_HW_REG_TYPE_UW 2
> #define BRW_HW_REG_TYPE_W 3
> #define BRW_HW_REG_TYPE_F 7
> +#define GEN8_HW_REG_TYPE_UQ 8
> +#define GEN8_HW_REG_TYPE_Q 9
>
> #define BRW_HW_REG_NON_IMM_TYPE_UB 4
> #define BRW_HW_REG_NON_IMM_TYPE_B 5
> #define GEN7_HW_REG_NON_IMM_TYPE_DF 6
> +#define GEN8_HW_REG_NON_IMM_TYPE_HF 10
>
> #define BRW_HW_REG_IMM_TYPE_UV 4 /* Gen6+ packed unsigned immediate vector
> */
> #define BRW_HW_REG_IMM_TYPE_VF 5 /* packed float immediate vector */
> #define BRW_HW_REG_IMM_TYPE_V 6 /* packed int imm. vector; uword dest only
> */
> +#define GEN8_HW_REG_IMM_TYPE_DF 10
> +#define GEN8_HW_REG_IMM_TYPE_HF 11
>
> /* SNB adds 3-src instructions (MAD and LRP) that only operate on floats, so
> * the types were implied. IVB adds BFE and BFI2 that operate on doublewords
> diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
> b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> index 90fde1d..c653828 100644
> --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
> +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> @@ -122,10 +122,14 @@ brw_reg_type_to_hw_type(const struct brw_context *brw,
> [BRW_REGISTER_TYPE_UV] = BRW_HW_REG_IMM_TYPE_UV,
> [BRW_REGISTER_TYPE_VF] = BRW_HW_REG_IMM_TYPE_VF,
> [BRW_REGISTER_TYPE_V] = BRW_HW_REG_IMM_TYPE_V,
> - [BRW_REGISTER_TYPE_DF] = -1,
> + [BRW_REGISTER_TYPE_DF] = GEN8_HW_REG_IMM_TYPE_DF,
> + [BRW_REGISTER_TYPE_HF] = GEN8_HW_REG_IMM_TYPE_HF,
> + [BRW_REGISTER_TYPE_UQ] = GEN8_HW_REG_TYPE_UQ,
> + [BRW_REGISTER_TYPE_Q] = GEN8_HW_REG_TYPE_Q,
> };
> assert(type < ARRAY_SIZE(imm_hw_types));
> assert(imm_hw_types[type] != -1);
> + assert(brw->gen >= 8 || type < BRW_REGISTER_TYPE_DF);
> return imm_hw_types[type];
> } else {
> /* Non-immediate registers */
> @@ -141,10 +145,14 @@ brw_reg_type_to_hw_type(const struct brw_context *brw,
> [BRW_REGISTER_TYPE_VF] = -1,
> [BRW_REGISTER_TYPE_V] = -1,
> [BRW_REGISTER_TYPE_DF] = GEN7_HW_REG_NON_IMM_TYPE_DF,
> + [BRW_REGISTER_TYPE_HF] = GEN8_HW_REG_NON_IMM_TYPE_HF,
> + [BRW_REGISTER_TYPE_UQ] = GEN8_HW_REG_TYPE_UQ,
> + [BRW_REGISTER_TYPE_Q] = GEN8_HW_REG_TYPE_Q,
> };
> assert(type < ARRAY_SIZE(hw_types));
> assert(hw_types[type] != -1);
> assert(brw->gen >= 7 || type < BRW_REGISTER_TYPE_DF);
> + assert(brw->gen >= 8 || type < BRW_REGISTER_TYPE_HF);
> return hw_types[type];
> }
> }
> diff --git a/src/mesa/drivers/dri/i965/brw_reg.h
> b/src/mesa/drivers/dri/i965/brw_reg.h
> index 1e6ed6b..9e798df 100644
> --- a/src/mesa/drivers/dri/i965/brw_reg.h
> +++ b/src/mesa/drivers/dri/i965/brw_reg.h
> @@ -107,6 +107,11 @@ enum brw_reg_type {
> /** @} */
>
> BRW_REGISTER_TYPE_DF, /* Gen7+ (no immediates until Gen8+) */
> +
> + /* Gen8+ */
> + BRW_REGISTER_TYPE_HF,
> + BRW_REGISTER_TYPE_UQ,
> + BRW_REGISTER_TYPE_Q,
> };
>
> unsigned brw_reg_type_to_hw_type(const struct brw_context *brw,
> --
> 1.8.4.4
>
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