Now that we have a helper function that handles the PIPE_CONTROL
variations between the various platforms, these are basically the same.
Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/brw_context.h | 1 +
src/mesa/drivers/dri/i965/brw_queryobj.c | 12 +++++++-----
src/mesa/drivers/dri/i965/gen6_queryobj.c | 20 ++------------------
3 files changed, 10 insertions(+), 23 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index f04a2c9..47f342b 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1564,6 +1564,7 @@ void brw_emit_query_end(struct brw_context *brw);
/** gen6_queryobj.c */
void gen6_init_queryobj_functions(struct dd_function_table *functions);
void brw_write_timestamp(struct brw_context *brw, drm_intel_bo *bo, int idx);
+void brw_write_depth_count(struct brw_context *brw, drm_intel_bo *bo, int idx);
void brw_store_register_mem64(struct brw_context *brw,
drm_intel_bo *bo, uint32_t reg, int idx);
diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c
b/src/mesa/drivers/dri/i965/brw_queryobj.c
index 31f1cab..e669047 100644
--- a/src/mesa/drivers/dri/i965/brw_queryobj.c
+++ b/src/mesa/drivers/dri/i965/brw_queryobj.c
@@ -62,10 +62,12 @@ brw_write_timestamp(struct brw_context *brw, drm_intel_bo
*query_bo, int idx)
/**
* Emit PIPE_CONTROLs to write the PS_DEPTH_COUNT register into a buffer.
*/
-static void
-write_depth_count(struct brw_context *brw, drm_intel_bo *query_bo, int idx)
+void
+brw_write_depth_count(struct brw_context *brw, drm_intel_bo *query_bo, int idx)
{
- assert(brw->gen < 6);
+ /* Emit Sandybridge workaround flush: */
+ if (brw->gen == 6)
+ intel_emit_post_sync_nonzero_flush(brw);
brw_emit_pipe_control_write(brw,
PIPE_CONTROL_WRITE_DEPTH_COUNT
@@ -430,7 +432,7 @@ brw_emit_query_begin(struct brw_context *brw)
ensure_bo_has_space(ctx, query);
- write_depth_count(brw, query->bo, query->last_index * 2);
+ brw_write_depth_count(brw, query->bo, query->last_index * 2);
brw->query.begin_emitted = true;
}
@@ -452,7 +454,7 @@ brw_emit_query_end(struct brw_context *brw)
if (!brw->query.begin_emitted)
return;
- write_depth_count(brw, query->bo, query->last_index * 2 + 1);
+ brw_write_depth_count(brw, query->bo, query->last_index * 2 + 1);
brw->query.begin_emitted = false;
query->last_index++;
diff --git a/src/mesa/drivers/dri/i965/gen6_queryobj.c
b/src/mesa/drivers/dri/i965/gen6_queryobj.c
index 5257127..a95441f 100644
--- a/src/mesa/drivers/dri/i965/gen6_queryobj.c
+++ b/src/mesa/drivers/dri/i965/gen6_queryobj.c
@@ -39,22 +39,6 @@
#include "intel_batchbuffer.h"
#include "intel_reg.h"
-/**
- * Emit PIPE_CONTROLs to write the PS_DEPTH_COUNT register into a buffer.
- */
-static void
-write_depth_count(struct brw_context *brw, drm_intel_bo *query_bo, int idx)
-{
- /* Emit Sandybridge workaround flush: */
- if (brw->gen == 6)
- intel_emit_post_sync_nonzero_flush(brw);
-
- brw_emit_pipe_control_write(brw,
- PIPE_CONTROL_WRITE_DEPTH_COUNT
- | PIPE_CONTROL_DEPTH_STALL,
- query_bo, idx * sizeof(uint64_t), 0, 0);
-}
-
/*
* Write an arbitrary 64-bit register to a buffer via MI_STORE_REGISTER_MEM.
*
@@ -239,7 +223,7 @@ gen6_begin_query(struct gl_context *ctx, struct
gl_query_object *q)
case GL_ANY_SAMPLES_PASSED:
case GL_ANY_SAMPLES_PASSED_CONSERVATIVE:
case GL_SAMPLES_PASSED_ARB:
- write_depth_count(brw, query->bo, 0);
+ brw_write_depth_count(brw, query->bo, 0);
break;
case GL_PRIMITIVES_GENERATED:
@@ -278,7 +262,7 @@ gen6_end_query(struct gl_context *ctx, struct
gl_query_object *q)
case GL_ANY_SAMPLES_PASSED:
case GL_ANY_SAMPLES_PASSED_CONSERVATIVE:
case GL_SAMPLES_PASSED_ARB:
- write_depth_count(brw, query->bo, 1);
+ brw_write_depth_count(brw, query->bo, 1);
break;
case GL_PRIMITIVES_GENERATED:
--
1.8.4.4
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