On 3 December 2013 13:12, Chad Versace <chad.vers...@linux.intel.com> wrote:
> The BSpec states that the aligment for the non-msrt clear rectangle must
> be doubled; the BSpec does not restricit the workaround to specific
> hardware.
>
> Commit 9a1a67b applied the workaround to Haswell GT3. Commit 8b659ce
> expanded the workaround to all Haswell variants. This commit expands it
> to all hardware.
>
> No Piglit regressions on Ivybridge 0x0166. No fixes either.
>
> I know no Ivybridge nor Baytrail bug related to this workaround.
> However, the BSpec says the extra alignment is required, so let's do it.
>
> v2: Apply to all hardware, not just gen7.
>
> CC: "9.2, 10.0" <mesa-sta...@lists.freedesktop.org>
> CC: Anuj Phogat <anuj.pho...@gmail.com>
> CC: Paul Berry <stereotype...@gmail.com>
> Signed-off-by: Chad Versace <chad.vers...@linux.intel.com>
>
Looks correct to me.
Reviewed-by: Paul Berry <stereotype...@gmail.com>
> ---
> src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 35
> +++++++++------------------
> 1 file changed, 11 insertions(+), 24 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
> b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
> index 3f096b5..1904bde 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
> @@ -265,30 +265,17 @@
> brw_blorp_clear_params::brw_blorp_clear_params(struct brw_context *brw,
> x_align *= 16;
> y_align *= 32;
>
> - if (brw->is_haswell) {
> - /* From BSpec: 3D-Media-GPGPU Engine > 3D Pipeline > Pixel >
> Pixel
> - * Backend > MCS Buffer for Render Target(s) [DevIVB+] > Table
> "Color
> - * Clear of Non-MultiSampled Render Target Restrictions":
> - *
> - * [IVB, VLVT, HSW]: Clear rectangle must be aligned to two
> times
> - * the number of pixels in the table shown below... x_align,
> - * y_align values computed above are the relevant entries in
> the
> - * referred table.
> - *
> - * We apply the workaround to only Haswell because (a) we
> suspect that
> - * is the only hardware where it is actually required and (b) we
> - * haven't yet validated the workaround for the other hardware.
> - */
> - x0 = ROUND_DOWN_TO(x0, 2 * x_align);
> - y0 = ROUND_DOWN_TO(y0, 2 * y_align);
> - x1 = ALIGN(x1, 2 * x_align);
> - y1 = ALIGN(y1, 2 * y_align);
> - } else {
> - x0 = ROUND_DOWN_TO(x0, x_align);
> - y0 = ROUND_DOWN_TO(y0, y_align);
> - x1 = ALIGN(x1, x_align);
> - y1 = ALIGN(y1, y_align);
> - }
> + /* From BSpec: 3D-Media-GPGPU Engine > 3D Pipeline > Pixel > Pixel
> + * Backend > MCS Buffer for Render Target(s) [DevIVB+] > Table
> "Color
> + * Clear of Non-MultiSampled Render Target Restrictions":
> + *
> + * Clear rectangle must be aligned to two times the number of
> pixels in
> + * the table shown below due to 16x16 hashing across the slice.
> + */
> + x0 = ROUND_DOWN_TO(x0, 2 * x_align);
> + y0 = ROUND_DOWN_TO(y0, 2 * y_align);
> + x1 = ALIGN(x1, 2 * x_align);
> + y1 = ALIGN(y1, 2 * y_align);
>
> /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
> * Target(s)", beneath the "Fast Color Clear" bullet (p327):
> --
> 1.8.4
>
>
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