Until now it was only being taken into account in the VEC4 back-end
but not in the FS back-end. Do it in both cases.
---
src/mesa/drivers/dri/i965/brw_fs.h | 2 +-
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 10 ++++++----
src/mesa/drivers/dri/i965/brw_shader.h | 7 ++++---
3 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index 2c36d9f..f918f7e 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -615,4 +615,4 @@ bool brw_do_channel_expressions(struct exec_list
*instructions);
bool brw_do_vector_splitting(struct exec_list *instructions);
bool brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog);
-struct brw_reg brw_reg_from_fs_reg(fs_reg *reg);
+struct brw_reg brw_reg_from_fs_reg(fs_reg *reg, unsigned dispatch_width);
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index 8d310a1..1de59eb 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -981,8 +981,9 @@ static uint32_t brw_file_from_reg(fs_reg *reg)
}
struct brw_reg
-brw_reg_from_fs_reg(fs_reg *reg)
+brw_reg_from_fs_reg(fs_reg *reg, unsigned dispatch_width)
{
+ const int reg_size = 4 * dispatch_width;
struct brw_reg brw_reg;
switch (reg->file) {
@@ -996,7 +997,8 @@ brw_reg_from_fs_reg(fs_reg *reg)
}
brw_reg = retype(brw_reg, reg->type);
- brw_reg = byte_offset(brw_reg, reg->subreg_offset);
+ brw_reg = byte_offset(brw_reg, (reg->subreg_offset +
+ reg->reg_offset * reg_size));
break;
case IMM:
switch (reg->type) {
@@ -1349,7 +1351,7 @@ fs_generator::generate_code(exec_list *instructions)
}
for (unsigned int i = 0; i < 3; i++) {
- src[i] = brw_reg_from_fs_reg(&inst->src[i]);
+ src[i] = brw_reg_from_fs_reg(&inst->src[i], dispatch_width);
/* The accumulator result appears to get used for the
* conditional modifier generation. When negating a UD
@@ -1361,7 +1363,7 @@ fs_generator::generate_code(exec_list *instructions)
inst->src[i].type != BRW_REGISTER_TYPE_UD ||
!inst->src[i].negate);
}
- dst = brw_reg_from_fs_reg(&inst->dst);
+ dst = brw_reg_from_fs_reg(&inst->dst, dispatch_width);
brw_set_conditionalmod(p, inst->conditional_mod);
brw_set_predicate_control(p, inst->predicate);
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h
b/src/mesa/drivers/dri/i965/brw_shader.h
index f284389..d1357ce 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -61,9 +61,10 @@ public:
/**
* Offset from the start of the contiguous register block.
*
- * For pre-register-allocation GRFs, this is in units of a float per pixel
- * (1 hardware register for SIMD8 mode, or 2 registers for SIMD16 mode).
- * For uniforms, this is in units of 1 float.
+ * For pre-register-allocation GRFs and MRFs, this is in units of a
+ * float per pixel (1 hardware register for SIMD8 mode, or 2
+ * registers for SIMD16 mode). For uniforms, this is in units of 1
+ * float.
*/
int reg_offset;
--
1.8.3.4
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