[Mesa-dev] [PATCH 7/9] i965: introduce new FS IR opcode for simd16 replicated write

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
 src/mesa/drivers/dri/i965/brw_defines.h           | 1 +
 src/mesa/drivers/dri/i965/brw_fs.cpp              | 1 +
 src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 1 +
 src/mesa/drivers/dri/i965/brw_shader.cpp          | 2 ++
 4 files changed, 5 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
b/src/mesa/drivers/dri/i965/brw_defines.h
index 597d3b2..9eb8503 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -752,6 +752,7 @@ enum opcode {
     * instructions.
     */
    FS_OPCODE_FB_WRITE = 128,
+   FS_OPCODE_FB_WRITE_SIMD16_REPLICATED,
    SHADER_OPCODE_RCP,
    SHADER_OPCODE_RSQ,
    SHADER_OPCODE_SQRT,
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 261f906..42a3c8c 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -773,6 +773,7 @@ fs_visitor::implied_mrf_writes(fs_inst *inst)
    case SHADER_OPCODE_LOD:
       return 1;
    case FS_OPCODE_FB_WRITE:
+   case FS_OPCODE_FB_WRITE_SIMD16_REPLICATED:
       return 2;
    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
    case SHADER_OPCODE_GEN4_SCRATCH_READ:
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index 8567afd..8b252af 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -285,6 +285,7 @@ fs_visitor::setup_payload_interference(struct ra_graph *g,
       /* Special case instructions which have extra implied registers used. */
       switch (inst->opcode) {
       case FS_OPCODE_FB_WRITE:
+      case FS_OPCODE_FB_WRITE_SIMD16_REPLICATED:
          /* We could omit this for the !inst->header_present case, except that
           * the simulator apparently incorrectly reads from g0/g1 instead of
           * sideband.  It also really freaks out driver developers to see g0
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp 
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index ddb4524..702c25b 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -413,6 +413,8 @@ brw_instruction_name(enum opcode op)
    switch (op) {
    case FS_OPCODE_FB_WRITE:
       return "fb_write";
+   case FS_OPCODE_FB_WRITE_SIMD16_REPLICATED:
+      return "fb_write_simd16_replicated";
 
    case SHADER_OPCODE_RCP:
       return "rcp";
-- 
1.8.3.1

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