XXX: Gen6+ needs to be predicated on register writes.
our register write checking function doesn't work on Gen6.
(this patch will be replaced; I'd just like to send the others up for
review sooner rather than later)
Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
Cc: Eric Anholt <e...@anholt.net>
Cc: Carl Worth <cwo...@cworth.org>
Cc: Juha-Pekka Heikkilä <juha-pekka.heikk...@intel.com>
---
src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index 62c0b15..2b07fc6 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -222,6 +222,7 @@ intelInitExtensions(struct gl_context *ctx)
ctx->Extensions.EXT_timer_query = true;
ctx->Extensions.EXT_shader_integer_mix = ctx->Const.GLSLVersion >= 130;
ctx->Extensions.ARB_texture_query_levels = ctx->Const.GLSLVersion >= 130;
+ ctx->Extensions.AMD_performance_monitor = true;
}
if (brw->gen >= 7) {
--
1.8.3.2
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