This hasn't been true since SIMD16 mode was added.
---
src/mesa/drivers/dri/i965/brw_fs.h | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index 5b78313..5f331e1 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -88,9 +88,11 @@ public:
*/
int reg;
/**
- * For virtual registers, this is a hardware register offset from
- * the start of the register block (for example, a constant index
- * in an array access).
+ * Offset from the start of the contiguous register block.
+ *
+ * For pre-register-allocation GRFs, this is in units of a float per pixel
+ * (1 hardware register for SIMD8 mode, or 2 registers for SIMD16 mode).
+ * For uniforms, this is in units of 1 float.
*/
int reg_offset;
/** Register type. BRW_REGISTER_TYPE_* */
--
1.8.4.rc3
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