3rd patch is reviewed-by:Vincent Lejeune<vljn at ovi.com>
The first one
>Subject: [PATCH 1/4] R600/SI: Mark the EXEC register as reserved
>
>This prevents the machine verifier from complaining about uses of
>an undefined physical register.
>---
> lib/Target/R600/SIRegisterInfo.cpp | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-) >diff --git
> a/lib/Target/R600/SIRegisterInfo.cpp b/lib/Target/R600/SIRegisterInfo.cpp
>index 5d12564..279ff33 100644
>--- a/lib/Target/R600/SIRegisterInfo.cpp
>+++ b/lib/Target/R600/SIRegisterInfo.cpp
>@@ -25,7 +25,8 @@ SIRegisterInfo::SIRegisterInfo(AMDGPUTargetMachine &tm) >
>BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
> BitVector Reserved(getNumRegs());
>- return Reserved;
>+ Reserved.set(AMDGPU::EXEC);
>+ return Reserved;
> }
looks like a tab space increment there.
With this fixed, this patch is reviewed-by:Vincent Lejeune<vljn at ovi.com>
I'd like somebody else to have a look at the 2 others patches, I'm not familiar
enough with SI isa for now.
----- Mail original -----
> De : Tom Stellard <t...@stellard.net>
> À : llvm-comm...@cs.uiuc.edu
> Cc : mesa-dev@lists.freedesktop.org
> Envoyé le : Vendredi 4 octobre 2013 2h36
> Objet : PATCH: R600/SI: Enable the verifier on most lit tests
>
> Hi,
>
> I would like to start using the machine verifier to help catch compiler
> bugs. I think it will be especially useful for making sure all our
> instructions have legal operands. The attached patches fix some simple
> machine verifier errors and enable it for most lit tests.
>
> Unfortunately, we cannot enable the machine verifier on tests that have
> branches, because the way IF and ELSE instructions are selected leaves us
> with a copy instruction following the IF and ELSE terminators, which
> violates one of the verifier rules.
>
> -Tom
>
> _______________________________________________
> llvm-commits mailing list
> llvm-comm...@cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
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