On Mon, Aug 12, 2013 at 3:07 PM, <ville.syrj...@linux.intel.com> wrote: > From: Ville Syrjälä <ville.syrj...@linux.intel.com> > > IVB/BYT also has the same L3 cacheability control in MOCS as HSW, > so let's make use of it.
According to the discussion we had on #intel-gfx a few weeks ago, on IVB all Mesa memory is already marked as cached in DRM allocated PTEs. So this should not have any effect. Or I'm misunderstanding something. As I understand, marking everything uncacheable and then marking just certain things cacheable could make a difference (since AFAIK, you can't mark select regions as uncacheable after you mark PTEs as cacheable on IVB). Can somebody more knowledgeable comment? _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
