On Sat, Aug 10, 2013 at 08:50:31PM +0200, Marek Olšák wrote:
> Signed-off-by: Marek Olšák <marek.ol...@amd.com>
You will need to add a test case to this commit, but otherwise the whole
series is:
Reviewed-by: Tom Stellard <t...@stellard.net>
Do you have commit access yet?
-Tom
> ---
> lib/Target/R600/SIInstructions.td | 5 +++++
> lib/Target/R600/SIRegisterInfo.td | 4 ++--
> 2 files changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/lib/Target/R600/SIInstructions.td
> b/lib/Target/R600/SIInstructions.td
> index d941035..be2e290 100644
> --- a/lib/Target/R600/SIInstructions.td
> +++ b/lib/Target/R600/SIInstructions.td
> @@ -1506,6 +1506,11 @@ def : BitConvert <v2i32, v2f32, VReg_64>;
> def : BitConvert <v4f32, v4i32, VReg_128>;
> def : BitConvert <v4i32, v4f32, VReg_128>;
>
> +def : BitConvert <v8i32, v32i8, SReg_256>;
> +def : BitConvert <v32i8, v8i32, SReg_256>;
> +def : BitConvert <v8i32, v32i8, VReg_256>;
> +def : BitConvert <v32i8, v8i32, VReg_256>;
> +
> /********** =================== **********/
> /********** Src & Dst modifiers **********/
> /********** =================== **********/
> diff --git a/lib/Target/R600/SIRegisterInfo.td
> b/lib/Target/R600/SIRegisterInfo.td
> index 292b9d2..82d1e71 100644
> --- a/lib/Target/R600/SIRegisterInfo.td
> +++ b/lib/Target/R600/SIRegisterInfo.td
> @@ -159,7 +159,7 @@ def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, i1],
> 64,
>
> def SReg_128 : RegisterClass<"AMDGPU", [v16i8, i128], 128, (add SGPR_128)>;
>
> -def SReg_256 : RegisterClass<"AMDGPU", [v32i8], 256, (add SGPR_256)>;
> +def SReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add
> SGPR_256)>;
>
> def SReg_512 : RegisterClass<"AMDGPU", [v64i8], 512, (add SGPR_512)>;
>
> @@ -174,7 +174,7 @@ def VReg_96 : RegisterClass<"AMDGPU", [untyped], 96, (add
> VGPR_96)> {
>
> def VReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32], 128, (add VGPR_128)>;
>
> -def VReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 256, (add VGPR_256)>;
> +def VReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add
> VGPR_256)>;
>
> def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 512, (add
> VGPR_512)>;
>
> --
> 1.8.1.2
>
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