On Fri, Aug 09, 2013 at 02:59:07PM +0200, Niels Ole Salscheider wrote:
> ---
This series is:
Reviewed-by: Tom Stellard <thomas.stell...@amd.com>
Your implementation of SITargetLowering::isFMAFasterThanFMulAndFAdd()
is correct for SI, not sure about Sea Islands, but we can always fix it
later. Feel free to commit these patches whenever you want.
-Tom
> lib/Target/R600/SIInstructions.td | 8 ++++++--
> test/CodeGen/R600/fma.ll | 31 +++++++++++++++++++++++++++++++
> 2 Dateien geändert, 37 Zeilen hinzugefügt(+), 2 Zeilen entfernt(-)
> create mode 100644 test/CodeGen/R600/fma.ll
>
> diff --git a/lib/Target/R600/SIInstructions.td
> b/lib/Target/R600/SIInstructions.td
> index dc41885..dc14609 100644
> --- a/lib/Target/R600/SIInstructions.td
> +++ b/lib/Target/R600/SIInstructions.td
> @@ -1007,8 +1007,12 @@ def V_BFE_U32 : VOP3_32 <0x00000148, "V_BFE_U32", []>;
> def V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32", []>;
> def V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32", []>;
> defm : BFIPatterns <V_BFI_B32>;
> -def V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32", []>;
> -def V_FMA_F64 : VOP3_64 <0x0000014c, "V_FMA_F64", []>;
> +def V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32",
> + [(set f32:$dst, (fma f32:$src0, f32:$src1, f32:$src2))]
> +>;
> +def V_FMA_F64 : VOP3_64 <0x0000014c, "V_FMA_F64",
> + [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))]
> +>;
> //def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>;
> def V_ALIGNBIT_B32 : VOP3_32 <0x0000014e, "V_ALIGNBIT_B32", []>;
> def : ROTRPattern <V_ALIGNBIT_B32>;
> diff --git a/test/CodeGen/R600/fma.ll b/test/CodeGen/R600/fma.ll
> new file mode 100644
> index 0000000..afef970
> --- /dev/null
> +++ b/test/CodeGen/R600/fma.ll
> @@ -0,0 +1,31 @@
> +; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
> +
> +; CHECK: @fma_f32
> +; CHECK: V_FMA_F32 {{VGPR[0-9]+, VGPR[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
> +
> +define void @fma_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
> + float addrspace(1)* %in2, float addrspace(1)* %in3) {
> + %r0 = load float addrspace(1)* %in1
> + %r1 = load float addrspace(1)* %in2
> + %r2 = load float addrspace(1)* %in3
> + %r3 = tail call float @llvm.fma.f32(float %r0, float %r1, float %r2)
> + store float %r3, float addrspace(1)* %out
> + ret void
> +}
> +
> +declare float @llvm.fma.f32(float, float, float)
> +
> +; CHECK: @fma_f64
> +; CHECK: V_FMA_F64 {{VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+,
> VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+}}
> +
> +define void @fma_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
> + double addrspace(1)* %in2, double addrspace(1)* %in3) {
> + %r0 = load double addrspace(1)* %in1
> + %r1 = load double addrspace(1)* %in2
> + %r2 = load double addrspace(1)* %in3
> + %r3 = tail call double @llvm.fma.f64(double %r0, double %r1, double %r2)
> + store double %r3, double addrspace(1)* %out
> + ret void
> +}
> +
> +declare double @llvm.fma.f64(double, double, double)
> --
> 1.7.11.7
>
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