LLVM revision 187139 ('Allocate local registers in order for optimal
coloring.') broke some derivative related piglit tests with the radeonsi
driver.
I'm attaching a diff between the bad and good generated code (as printed
with RADEON_DUMP_SHADERS=1) for the glsl-derivs test. The only
difference I can see is in which registers are used in which order.
I wonder if we might be missing S_WAITCNT after DS_READ/WRITE
instructions in some cases, but I haven't spotted any candidates for
that in the bad code which aren't there in the good code as well. Can
anyone else spot something I've missed?
Any other ideas?
--
Earthling Michel Dänzer | http://www.amd.com
Libre software enthusiast | Debian, X and DRI developer
--- /tmp/glsl-derivs.bad 2013-07-31 12:01:43.248405367 +0200
+++ /tmp/glsl-derivs.good 2013-07-31 12:03:22.640102890 +0200
@@ -605,40 +605,40 @@ BB#0: derived from LLVM BB %main_body
%M0<def> = S_MOV_B32 %SGPR6
%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>
- %VGPR2<def> = V_MUL_F32_e32 4.000000e+01, %VGPR2<kill>, %EXEC<imp-use>
- %VGPR3<def> = V_MBCNT_LO_U32_B32_e64 -1, 0, 0, 0, 0, 0, %EXEC<imp-use>
- %VGPR3<def> = V_MBCNT_HI_U32_B32_e32 -1, %VGPR3<kill>, %EXEC<imp-use>, %VGPR3_VGPR4<imp-def>
- %VGPR4<def> = V_ASHRREV_I32_e32 31, %VGPR3, %EXEC<imp-use>, %VGPR3_VGPR4<imp-use,kill>, %VGPR3_VGPR4<imp-def>
- %VGPR5_VGPR6<def> = V_LSHL_B64 %VGPR3_VGPR4, 2, %EXEC<imp-use>
- DS_WRITE_B32 %VGPR5, %VGPR5, %VGPR2<kill>, %VGPR2, 0, 0, %EXEC<imp-use>; mem:ST4[%28]
- %VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
- %VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
- %VGPR0<def> = V_MUL_F32_e32 4.000000e+01, %VGPR2<kill>, %EXEC<imp-use>
+ %VGPR6<def> = V_MUL_F32_e32 4.000000e+01, %VGPR2<kill>, %EXEC<imp-use>
+ %VGPR2<def> = V_MBCNT_LO_U32_B32_e64 -1, 0, 0, 0, 0, 0, %EXEC<imp-use>
+ %VGPR4<def> = V_MBCNT_HI_U32_B32_e32 -1, %VGPR2<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
+ %VGPR5<def> = V_ASHRREV_I32_e32 31, %VGPR4, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
+ %VGPR2_VGPR3<def> = V_LSHL_B64 %VGPR4_VGPR5, 2, %EXEC<imp-use>
+ DS_WRITE_B32 %VGPR2, %VGPR2, %VGPR6<kill>, %VGPR6, 0, 0, %EXEC<imp-use>; mem:ST4[%28]
+ %VGPR6<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
+ %VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
+ %VGPR0<def> = V_MUL_F32_e32 4.000000e+01, %VGPR6<kill>, %EXEC<imp-use>
%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%20](tbaa=!"const")
S_WAITCNT 127
%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 0
S_WAITCNT 127
%VGPR0<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR0<kill>, %EXEC<imp-use>
- %VGPR1<def> = V_AND_B32_e32 -4, %VGPR3, %EXEC<imp-use>, %VGPR3_VGPR4<imp-use,kill>, %VGPR1_VGPR2<imp-def>
- %VGPR3<def> = V_OR_B32_e32 1, %VGPR1, %EXEC<imp-use>, %VGPR3_VGPR4<imp-def>
- %VGPR4<def> = V_ASHRREV_I32_e32 31, %VGPR3, %EXEC<imp-use>, %VGPR3_VGPR4<imp-use,kill>, %VGPR3_VGPR4<imp-def>
- %VGPR3_VGPR4<def> = V_LSHL_B64 %VGPR3_VGPR4<kill>, 2, %EXEC<imp-use>
- %VGPR3<def> = DS_READ_B32 0, %VGPR3, %VGPR3, %VGPR3, 0, 0, %EXEC<imp-use>, %VGPR3_VGPR4<imp-use,kill>; mem:LD4[%32]
- %VGPR2<def> = V_ASHRREV_I32_e32 31, %VGPR1, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
- %VGPR7_VGPR8<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
- %VGPR4<def> = DS_READ_B32 0, %VGPR7, %VGPR7, %VGPR7, 0, 0, %EXEC<imp-use>; mem:LD4[%30]
- DS_WRITE_B32 %VGPR5, %VGPR5, %VGPR0, %VGPR0, 0, 0, %EXEC<imp-use>; mem:ST4[%49]
- %VGPR1<def> = V_OR_B32_e32 2, %VGPR1, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
- %VGPR2<def> = V_ASHRREV_I32_e32 31, %VGPR1, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
- %VGPR1_VGPR2<def> = V_LSHL_B64 %VGPR1_VGPR2<kill>, 2, %EXEC<imp-use>
- %VGPR1<def> = DS_READ_B32 0, %VGPR1, %VGPR1, %VGPR1, 0, 0, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>; mem:LD4[%53]
- %VGPR2<def> = DS_READ_B32 0, %VGPR7, %VGPR7, %VGPR7, 0, 0, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>; mem:LD4[%51]
- DS_WRITE_B32 %VGPR5, %VGPR5, %VGPR0, %VGPR0, 0, 0, %EXEC<imp-use>; mem:ST4[%49]
- DS_WRITE_B32 %VGPR5, %VGPR5, %VGPR0, %VGPR0, 0, 0, %EXEC<imp-use>; mem:ST4[%49]
- DS_WRITE_B32 %VGPR5, %VGPR5, %VGPR0<kill>, %VGPR0, 0, 0, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>; mem:ST4[%49]
+ %VGPR4<def> = V_AND_B32_e32 -4, %VGPR4, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
+ %VGPR6<def> = V_OR_B32_e32 1, %VGPR4, %EXEC<imp-use>, %VGPR6_VGPR7<imp-def>
+ %VGPR7<def> = V_ASHRREV_I32_e32 31, %VGPR6, %EXEC<imp-use>, %VGPR6_VGPR7<imp-use,kill>, %VGPR6_VGPR7<imp-def>
+ %VGPR6_VGPR7<def> = V_LSHL_B64 %VGPR6_VGPR7<kill>, 2, %EXEC<imp-use>
+ %VGPR1<def> = DS_READ_B32 0, %VGPR6, %VGPR6, %VGPR6, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7<imp-use,kill>; mem:LD4[%32]
+ %VGPR5<def> = V_ASHRREV_I32_e32 31, %VGPR4, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
+ %VGPR7_VGPR8<def> = V_LSHL_B64 %VGPR4_VGPR5, 2, %EXEC<imp-use>
+ %VGPR6<def> = DS_READ_B32 0, %VGPR7, %VGPR7, %VGPR7, 0, 0, %EXEC<imp-use>; mem:LD4[%30]
+ DS_WRITE_B32 %VGPR2, %VGPR2, %VGPR0, %VGPR0, 0, 0, %EXEC<imp-use>; mem:ST4[%49]
+ %VGPR4<def> = V_OR_B32_e32 2, %VGPR4, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
+ %VGPR5<def> = V_ASHRREV_I32_e32 31, %VGPR4, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
+ %VGPR4_VGPR5<def> = V_LSHL_B64 %VGPR4_VGPR5<kill>, 2, %EXEC<imp-use>
+ %VGPR4<def> = DS_READ_B32 0, %VGPR4, %VGPR4, %VGPR4, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>; mem:LD4[%53]
+ %VGPR5<def> = DS_READ_B32 0, %VGPR7, %VGPR7, %VGPR7, 0, 0, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>; mem:LD4[%51]
+ DS_WRITE_B32 %VGPR2, %VGPR2, %VGPR0, %VGPR0, 0, 0, %EXEC<imp-use>; mem:ST4[%49]
+ DS_WRITE_B32 %VGPR2, %VGPR2, %VGPR0, %VGPR0, 0, 0, %EXEC<imp-use>; mem:ST4[%49]
+ DS_WRITE_B32 %VGPR2, %VGPR2, %VGPR0<kill>, %VGPR0, 0, 0, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>; mem:ST4[%49]
S_WAITCNT 127
- %VGPR0<def> = V_SUB_F32_e32 %VGPR3<kill>, %VGPR4<kill>, %EXEC<imp-use>
- %VGPR1<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR2<kill>, %EXEC<imp-use>
+ %VGPR0<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR6<kill>, %EXEC<imp-use>
+ %VGPR1<def> = V_SUB_F32_e32 %VGPR4<kill>, %VGPR5<kill>, %EXEC<imp-use>
%VGPR2<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
%VGPR3<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
EXP 15, 0, 0, 1, 1, %VGPR0<kill>, %VGPR1<kill>, %VGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use,kill>
@@ -652,56 +652,56 @@ befc03c1
befc0306
c8080000
c8090001
-100404ff
+100c04ff
42200000
-d2460003
+d2460002
020100c1
-480606c1
-3008069f
-d2c20005
-02010503
-d8360000
-00020205
-c8080100
-c8090101
-100004ff
+480804c1
+300a089f
+d2c20002
+02010504
+d8340000
+00060602
+c8180100
+c8190101
+10000cff
42200000
c0800100
bf8c007f
c2000100
bf8c007f
10000000
-360206c4
-38060281
-3008069f
-d2c20003
-02010503
+360808c4
+380c0881
+300e0c9f
+d2c20006
+02010506
d8d80000
-03030303
-3004029f
+01060606
+300a089f
d2c20007
-02010501
+02010504
d8d80000
-04070707
-d8360000
-00000005
-38020282
-3004029f
-d2c20001
-02010501
+06070707
+d8340000
+00000002
+38080882
+300a089f
+d2c20004
+02010504
d8d80000
-01010101
+04040404
d8d80000
-02070707
-d8360000
-00000005
-d8360000
-00000005
-d8360000
-00000005
+05070707
+d8340000
+00000002
+d8340000
+00000002
+d8340000
+00000002
bf8c007f
-08000903
-08020501
+08000d01
+08020b04
7e0402f2
7e060280
f800180f
@@ -1474,40 +1474,40 @@ BB#0: derived from LLVM BB %main_body
%M0<def> = S_MOV_B32 %SGPR6
%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>
- %VGPR2<def> = V_MUL_F32_e32 4.000000e+01, %VGPR2<kill>, %EXEC<imp-use>
- %VGPR3<def> = V_MBCNT_LO_U32_B32_e64 -1, 0, 0, 0, 0, 0, %EXEC<imp-use>
- %VGPR3<def> = V_MBCNT_HI_U32_B32_e32 -1, %VGPR3<kill>, %EXEC<imp-use>, %VGPR3_VGPR4<imp-def>
- %VGPR4<def> = V_ASHRREV_I32_e32 31, %VGPR3, %EXEC<imp-use>, %VGPR3_VGPR4<imp-use,kill>, %VGPR3_VGPR4<imp-def>
- %VGPR5_VGPR6<def> = V_LSHL_B64 %VGPR3_VGPR4, 2, %EXEC<imp-use>
- DS_WRITE_B32 %VGPR5, %VGPR5, %VGPR2<kill>, %VGPR2, 0, 0, %EXEC<imp-use>; mem:ST4[%28]
- %VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
- %VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
- %VGPR0<def> = V_MUL_F32_e32 4.000000e+01, %VGPR2<kill>, %EXEC<imp-use>
+ %VGPR6<def> = V_MUL_F32_e32 4.000000e+01, %VGPR2<kill>, %EXEC<imp-use>
+ %VGPR2<def> = V_MBCNT_LO_U32_B32_e64 -1, 0, 0, 0, 0, 0, %EXEC<imp-use>
+ %VGPR4<def> = V_MBCNT_HI_U32_B32_e32 -1, %VGPR2<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
+ %VGPR5<def> = V_ASHRREV_I32_e32 31, %VGPR4, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
+ %VGPR2_VGPR3<def> = V_LSHL_B64 %VGPR4_VGPR5, 2, %EXEC<imp-use>
+ DS_WRITE_B32 %VGPR2, %VGPR2, %VGPR6<kill>, %VGPR6, 0, 0, %EXEC<imp-use>; mem:ST4[%28]
+ %VGPR6<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
+ %VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
+ %VGPR0<def> = V_MUL_F32_e32 4.000000e+01, %VGPR6<kill>, %EXEC<imp-use>
%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%20](tbaa=!"const")
S_WAITCNT 127
%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 0
S_WAITCNT 127
%VGPR0<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR0<kill>, %EXEC<imp-use>
- %VGPR1<def> = V_AND_B32_e32 -4, %VGPR3, %EXEC<imp-use>, %VGPR3_VGPR4<imp-use,kill>, %VGPR1_VGPR2<imp-def>
- %VGPR3<def> = V_OR_B32_e32 1, %VGPR1, %EXEC<imp-use>, %VGPR3_VGPR4<imp-def>
- %VGPR4<def> = V_ASHRREV_I32_e32 31, %VGPR3, %EXEC<imp-use>, %VGPR3_VGPR4<imp-use,kill>, %VGPR3_VGPR4<imp-def>
- %VGPR3_VGPR4<def> = V_LSHL_B64 %VGPR3_VGPR4<kill>, 2, %EXEC<imp-use>
- %VGPR3<def> = DS_READ_B32 0, %VGPR3, %VGPR3, %VGPR3, 0, 0, %EXEC<imp-use>, %VGPR3_VGPR4<imp-use,kill>; mem:LD4[%32]
- %VGPR2<def> = V_ASHRREV_I32_e32 31, %VGPR1, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
- %VGPR7_VGPR8<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
- %VGPR4<def> = DS_READ_B32 0, %VGPR7, %VGPR7, %VGPR7, 0, 0, %EXEC<imp-use>; mem:LD4[%30]
- DS_WRITE_B32 %VGPR5, %VGPR5, %VGPR0, %VGPR0, 0, 0, %EXEC<imp-use>; mem:ST4[%49]
- %VGPR1<def> = V_OR_B32_e32 2, %VGPR1, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
- %VGPR2<def> = V_ASHRREV_I32_e32 31, %VGPR1, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
- %VGPR1_VGPR2<def> = V_LSHL_B64 %VGPR1_VGPR2<kill>, 2, %EXEC<imp-use>
- %VGPR1<def> = DS_READ_B32 0, %VGPR1, %VGPR1, %VGPR1, 0, 0, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>; mem:LD4[%53]
- %VGPR2<def> = DS_READ_B32 0, %VGPR7, %VGPR7, %VGPR7, 0, 0, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>; mem:LD4[%51]
- DS_WRITE_B32 %VGPR5, %VGPR5, %VGPR0, %VGPR0, 0, 0, %EXEC<imp-use>; mem:ST4[%49]
- DS_WRITE_B32 %VGPR5, %VGPR5, %VGPR0, %VGPR0, 0, 0, %EXEC<imp-use>; mem:ST4[%49]
- DS_WRITE_B32 %VGPR5, %VGPR5, %VGPR0<kill>, %VGPR0, 0, 0, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>; mem:ST4[%49]
+ %VGPR4<def> = V_AND_B32_e32 -4, %VGPR4, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
+ %VGPR6<def> = V_OR_B32_e32 1, %VGPR4, %EXEC<imp-use>, %VGPR6_VGPR7<imp-def>
+ %VGPR7<def> = V_ASHRREV_I32_e32 31, %VGPR6, %EXEC<imp-use>, %VGPR6_VGPR7<imp-use,kill>, %VGPR6_VGPR7<imp-def>
+ %VGPR6_VGPR7<def> = V_LSHL_B64 %VGPR6_VGPR7<kill>, 2, %EXEC<imp-use>
+ %VGPR1<def> = DS_READ_B32 0, %VGPR6, %VGPR6, %VGPR6, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7<imp-use,kill>; mem:LD4[%32]
+ %VGPR5<def> = V_ASHRREV_I32_e32 31, %VGPR4, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
+ %VGPR7_VGPR8<def> = V_LSHL_B64 %VGPR4_VGPR5, 2, %EXEC<imp-use>
+ %VGPR6<def> = DS_READ_B32 0, %VGPR7, %VGPR7, %VGPR7, 0, 0, %EXEC<imp-use>; mem:LD4[%30]
+ DS_WRITE_B32 %VGPR2, %VGPR2, %VGPR0, %VGPR0, 0, 0, %EXEC<imp-use>; mem:ST4[%49]
+ %VGPR4<def> = V_OR_B32_e32 2, %VGPR4, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
+ %VGPR5<def> = V_ASHRREV_I32_e32 31, %VGPR4, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
+ %VGPR4_VGPR5<def> = V_LSHL_B64 %VGPR4_VGPR5<kill>, 2, %EXEC<imp-use>
+ %VGPR4<def> = DS_READ_B32 0, %VGPR4, %VGPR4, %VGPR4, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>; mem:LD4[%53]
+ %VGPR5<def> = DS_READ_B32 0, %VGPR7, %VGPR7, %VGPR7, 0, 0, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>; mem:LD4[%51]
+ DS_WRITE_B32 %VGPR2, %VGPR2, %VGPR0, %VGPR0, 0, 0, %EXEC<imp-use>; mem:ST4[%49]
+ DS_WRITE_B32 %VGPR2, %VGPR2, %VGPR0, %VGPR0, 0, 0, %EXEC<imp-use>; mem:ST4[%49]
+ DS_WRITE_B32 %VGPR2, %VGPR2, %VGPR0<kill>, %VGPR0, 0, 0, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>; mem:ST4[%49]
S_WAITCNT 127
- %VGPR0<def> = V_SUB_F32_e32 %VGPR3<kill>, %VGPR4<kill>, %EXEC<imp-use>
- %VGPR1<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR2<kill>, %EXEC<imp-use>
+ %VGPR0<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR6<kill>, %EXEC<imp-use>
+ %VGPR1<def> = V_SUB_F32_e32 %VGPR4<kill>, %VGPR5<kill>, %EXEC<imp-use>
%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e64 0.000000e+00, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR1<kill>, %VGPR0, %VGPR1, %EXEC<imp-use,kill>
@@ -1521,56 +1521,56 @@ befc03c1
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