Hi Tom, I have verified that these patches, along with the previous one fix the errors that I was getting for SI. The test case from that FD.o bug still fails, but that's due to attempting to sign extend the v2i1/v4i1 result to v2i32/v4i32, which isn't necessary when doing vselect properly.
I've successfully run an int/int2/int4 min/max/clamp CL builtin test on my Pitcairn, so as far as I can tell, this is working correctly now. If we're concerned about the sign extension of boolean to 32-bit ints, I'd say that we should open a new bug for that. --Aaron On Tue, Jul 16, 2013 at 8:39 PM, Tom Stellard <t...@stellard.net> wrote: > Hi, > > The attached three patches along with this one should fix VSELECT on SI > as well. > > -Tom > > On Tue, Jul 16, 2013 at 05:12:40PM -0500, Aaron Watry wrote: >> Looks good to me. >> >> I've tested on Cedar (HD5400) with no OpenCL regressions, but cannot >> test on SI because SETCC still causes issues (see >> https://bugs.freedesktop.org/show_bug.cgi?id=66175). Once SETCC is >> fixed for SI, we should probably add SI-CHECK lines to vselect.ll >> >> --Aaron >> >> On Tue, Jul 16, 2013 at 2:15 PM, Tom Stellard <t...@stellard.net> wrote: >> > From: Tom Stellard <thomas.stell...@amd.com> >> > >> > --- >> > lib/Target/R600/AMDGPUISelLowering.cpp | 3 +++ >> > lib/Target/R600/R600ISelLowering.cpp | 3 --- >> > test/CodeGen/R600/vselect.ll | 30 ++++++++++++++++++++++++++++++ >> > 3 files changed, 33 insertions(+), 3 deletions(-) >> > >> > diff --git a/lib/Target/R600/AMDGPUISelLowering.cpp >> > b/lib/Target/R600/AMDGPUISelLowering.cpp >> > index 9891ad3..e93ddc4 100644 >> > --- a/lib/Target/R600/AMDGPUISelLowering.cpp >> > +++ b/lib/Target/R600/AMDGPUISelLowering.cpp >> > @@ -77,6 +77,8 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine >> > &TM) : >> > setOperationAction(ISD::UDIV, MVT::i32, Expand); >> > setOperationAction(ISD::UDIVREM, MVT::i32, Custom); >> > setOperationAction(ISD::UREM, MVT::i32, Expand); >> > + setOperationAction(ISD::VSELECT, MVT::v2f32, Expand); >> > + setOperationAction(ISD::VSELECT, MVT::v4f32, Expand); >> > >> > int types[] = { >> > (int)MVT::v2i32, >> > @@ -97,6 +99,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine >> > &TM) : >> > setOperationAction(ISD::SUB, VT, Expand); >> > setOperationAction(ISD::UDIV, VT, Expand); >> > setOperationAction(ISD::UREM, VT, Expand); >> > + setOperationAction(ISD::VSELECT, VT, Expand); >> > setOperationAction(ISD::XOR, VT, Expand); >> > } >> > } >> > diff --git a/lib/Target/R600/R600ISelLowering.cpp >> > b/lib/Target/R600/R600ISelLowering.cpp >> > index 7aef08a..1067b38 100644 >> > --- a/lib/Target/R600/R600ISelLowering.cpp >> > +++ b/lib/Target/R600/R600ISelLowering.cpp >> > @@ -67,9 +67,6 @@ R600TargetLowering::R600TargetLowering(TargetMachine >> > &TM) : >> > setOperationAction(ISD::SELECT, MVT::i32, Custom); >> > setOperationAction(ISD::SELECT, MVT::f32, Custom); >> > >> > - setOperationAction(ISD::VSELECT, MVT::v4i32, Expand); >> > - setOperationAction(ISD::VSELECT, MVT::v2i32, Expand); >> > - >> > // Legalize loads and stores to the private address space. >> > setOperationAction(ISD::LOAD, MVT::i32, Custom); >> > setOperationAction(ISD::LOAD, MVT::v2i32, Expand); >> > diff --git a/test/CodeGen/R600/vselect.ll b/test/CodeGen/R600/vselect.ll >> > index 3f08cec..79d896b 100644 >> > --- a/test/CodeGen/R600/vselect.ll >> > +++ b/test/CodeGen/R600/vselect.ll >> > @@ -14,6 +14,20 @@ entry: >> > ret void >> > } >> > >> > +;EG-CHECK: @test_select_v2f32 >> > +;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], >> > T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} >> > +;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], >> > T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} >> > + >> > +define void @test_select_v2f32(<2 x float> addrspace(1)* %out, <2 x >> > float> addrspace(1)* %in0, <2 x float> addrspace(1)* %in1) { >> > +entry: >> > + %0 = load <2 x float> addrspace(1)* %in0 >> > + %1 = load <2 x float> addrspace(1)* %in1 >> > + %cmp = fcmp one <2 x float> %0, %1 >> > + %result = select <2 x i1> %cmp, <2 x float> %0, <2 x float> %1 >> > + store <2 x float> %result, <2 x float> addrspace(1)* %out >> > + ret void >> > +} >> > + >> > ;EG-CHECK: @test_select_v4i32 >> > ;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], >> > T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} >> > ;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], >> > T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} >> > @@ -29,3 +43,19 @@ entry: >> > store <4 x i32> %result, <4 x i32> addrspace(1)* %out >> > ret void >> > } >> > + >> > +;EG-CHECK: @test_select_v4f32 >> > +;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], >> > T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} >> > +;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], >> > T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} >> > +;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], >> > T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} >> > +;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], >> > T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} >> > + >> > +define void @test_select_v4f32(<4 x float> addrspace(1)* %out, <4 x >> > float> addrspace(1)* %in0, <4 x float> addrspace(1)* %in1) { >> > +entry: >> > + %0 = load <4 x float> addrspace(1)* %in0 >> > + %1 = load <4 x float> addrspace(1)* %in1 >> > + %cmp = fcmp one <4 x float> %0, %1 >> > + %result = select <4 x i1> %cmp, <4 x float> %0, <4 x float> %1 >> > + store <4 x float> %result, <4 x float> addrspace(1)* %out >> > + ret void >> > +} >> > -- >> > 1.7.11.4 >> > >> > _______________________________________________ >> > mesa-dev mailing list >> > mesa-dev@lists.freedesktop.org >> > http://lists.freedesktop.org/mailman/listinfo/mesa-dev _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
